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1; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}3 4; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s5; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}6 7; CHECK-DAG: %[[Char:.*]] = OpTypeInt 8 08; CHECK-DAG: %[[CharVec2:.*]] = OpTypeVector %[[Char]] 29; CHECK-DAG: %[[CharVec3:.*]] = OpTypeVector %[[Char]] 310 11; CHECK-DAG: %[[Short:.*]] = OpTypeInt 16 012; CHECK-DAG: %[[ShortVec2:.*]] = OpTypeVector %[[Short]] 213; CHECK-DAG: %[[ShortVec3:.*]] = OpTypeVector %[[Short]] 314 15; CHECK-DAG: %[[Int:.*]] = OpTypeInt 32 016; CHECK-DAG: %[[IntVec2:.*]] = OpTypeVector %[[Int]] 217; CHECK-DAG: %[[IntVec3:.*]] = OpTypeVector %[[Int]] 318 19; CHECK-DAG: %[[Long:.*]] = OpTypeInt 64 020; CHECK-DAG: %[[LongVec2:.*]] = OpTypeVector %[[Long]] 221; CHECK-DAG: %[[LongVec3:.*]] = OpTypeVector %[[Long]] 322 23; CHECK: OpFunction24; CHECK: %[[Shuffle1:.*]] = OpVectorShuffle %[[CharVec2]] %[[#]] %[[#]] 1 0xFFFFFFFF25; CHECK: %[[Added1:.*]] = OpBitwiseAnd %[[CharVec2]] %[[#]] %[[#]]26; CHECK: %[[Vec2CharR:.*]] = OpCompositeExtract %[[Char]] %[[Added1]] 027; CHECK: OpReturnValue %[[Vec2CharR]]28; CHECK: OpFunctionEnd29 30; CHECK: OpFunction31; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]32; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 033; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 134; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 235; CHECK: %[[Vec3CharR1:.*]] = OpBitwiseAnd %[[Char]] %[[Vec3CharItem0]] %[[Vec3CharItem1]]36; CHECK: %[[Vec3CharR2:.*]] = OpBitwiseAnd %[[Char]] %[[Vec3CharR1]] %[[Vec3CharItem2]]37; CHECK: OpReturnValue %[[Vec3CharR2]]38; CHECK: OpFunctionEnd39 40; CHECK: OpFunction41; CHECK: %[[Shuffle1:.*]] = OpVectorShuffle %[[ShortVec2]] %[[#]] %[[#]] 1 0xFFFFFFFF42; CHECK: %[[Added1:.*]] = OpBitwiseAnd %[[ShortVec2]] %[[#]] %[[#]]43; CHECK: %[[Vec2ShortR:.*]] = OpCompositeExtract %[[Short]] %[[Added1]] 044; CHECK: OpReturnValue %[[Vec2ShortR]]45; CHECK: OpFunctionEnd46 47; CHECK: OpFunction48; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]49; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 050; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 151; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 252; CHECK: %[[Vec3ShortR1:.*]] = OpBitwiseAnd %[[Short]] %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]53; CHECK: %[[Vec3ShortR2:.*]] = OpBitwiseAnd %[[Short]] %[[Vec3ShortR1]] %[[Vec3ShortItem2]]54; CHECK: OpReturnValue %[[Vec3ShortR2]]55; CHECK: OpFunctionEnd56 57; CHECK: OpFunction58; CHECK: %[[Shuffle1:.*]] = OpVectorShuffle %[[IntVec2]] %[[#]] %[[#]] 1 0xFFFFFFFF59; CHECK: %[[Added1:.*]] = OpBitwiseAnd %[[IntVec2]] %[[#]] %[[#]]60; CHECK: %[[Vec2IntR:.*]] = OpCompositeExtract %[[Int]] %[[Added1]] 061; CHECK: OpReturnValue %[[Vec2IntR]]62; CHECK: OpFunctionEnd63 64; CHECK: OpFunction65; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]66; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 067; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 168; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 269; CHECK: %[[Vec3IntR1:.*]] = OpBitwiseAnd %[[Int]] %[[Vec3IntItem0]] %[[Vec3IntItem1]]70; CHECK: %[[Vec3IntR2:.*]] = OpBitwiseAnd %[[Int]] %[[Vec3IntR1]] %[[Vec3IntItem2]]71; CHECK: OpReturnValue %[[Vec3IntR2]]72; CHECK: OpFunctionEnd73 74; CHECK: OpFunction75; CHECK: %[[Shuffle1:.*]] = OpVectorShuffle %[[LongVec2]] %[[#]] %[[#]] 1 0xFFFFFFFF76; CHECK: %[[Added1:.*]] = OpBitwiseAnd %[[LongVec2]] %[[#]] %[[#]]77; CHECK: %[[Vec2LongR:.*]] = OpCompositeExtract %[[Long]] %[[Added1]] 078; CHECK: OpReturnValue %[[Vec2LongR]]79; CHECK: OpFunctionEnd80 81; CHECK: OpFunction82; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]83; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 084; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 185; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 286; CHECK: %[[Vec3LongR1:.*]] = OpBitwiseAnd %[[Long]] %[[Vec3LongItem0]] %[[Vec3LongItem1]]87; CHECK: %[[Vec3LongR2:.*]] = OpBitwiseAnd %[[Long]] %[[Vec3LongR1]] %[[Vec3LongItem2]]88; CHECK: OpReturnValue %[[Vec3LongR2]]89; CHECK: OpFunctionEnd90 91define spir_func i8 @test_vector_reduce_and_v2i8(<2 x i8> %v) {92entry:93 %res = call i8 @llvm.vector.reduce.and.v2i8(<2 x i8> %v)94 ret i8 %res95}96 97define spir_func i8 @test_vector_reduce_and_v3i8(<3 x i8> %v) {98entry:99 %res = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %v)100 ret i8 %res101}102 103define spir_func i8 @test_vector_reduce_and_v4i8(<4 x i8> %v) {104entry:105 %res = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %v)106 ret i8 %res107}108 109define spir_func i8 @test_vector_reduce_and_v8i8(<8 x i8> %v) {110entry:111 %res = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %v)112 ret i8 %res113}114 115define spir_func i8 @test_vector_reduce_and_v16i8(<16 x i8> %v) {116entry:117 %res = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %v)118 ret i8 %res119}120 121define spir_func i16 @test_vector_reduce_and_v2i16(<2 x i16> %v) {122entry:123 %res = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %v)124 ret i16 %res125}126 127define spir_func i16 @test_vector_reduce_and_v3i16(<3 x i16> %v) {128entry:129 %res = call i16 @llvm.vector.reduce.and.v3i16(<3 x i16> %v)130 ret i16 %res131}132 133define spir_func i16 @test_vector_reduce_and_v4i16(<4 x i16> %v) {134entry:135 %res = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %v)136 ret i16 %res137}138 139define spir_func i16 @test_vector_reduce_and_v8i16(<8 x i16> %v) {140entry:141 %res = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %v)142 ret i16 %res143}144 145define spir_func i16 @test_vector_reduce_and_v16i16(<16 x i16> %v) {146entry:147 %res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v)148 ret i16 %res149}150 151 152define spir_func i32 @test_vector_reduce_and_v2i32(<2 x i32> %v) {153entry:154 %res = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %v)155 ret i32 %res156}157 158define spir_func i32 @test_vector_reduce_and_v3i32(<3 x i32> %v) {159entry:160 %res = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %v)161 ret i32 %res162}163 164define spir_func i32 @test_vector_reduce_and_v4i32(<4 x i32> %v) {165entry:166 %res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %v)167 ret i32 %res168}169 170define spir_func i32 @test_vector_reduce_and_v8i32(<8 x i32> %v) {171entry:172 %res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v)173 ret i32 %res174}175 176define spir_func i32 @test_vector_reduce_and_v16i32(<16 x i32> %v) {177entry:178 %res = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %v)179 ret i32 %res180}181 182define spir_func i64 @test_vector_reduce_and_v2i64(<2 x i64> %v) {183entry:184 %res = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %v)185 ret i64 %res186}187 188define spir_func i64 @test_vector_reduce_and_v3i64(<3 x i64> %v) {189entry:190 %res = call i64 @llvm.vector.reduce.and.v3i64(<3 x i64> %v)191 ret i64 %res192}193 194define spir_func i64 @test_vector_reduce_and_v4i64(<4 x i64> %v) {195entry:196 %res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v)197 ret i64 %res198}199 200define spir_func i64 @test_vector_reduce_and_v8i64(<8 x i64> %v) {201entry:202 %res = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %v)203 ret i64 %res204}205 206define spir_func i64 @test_vector_reduce_and_v16i64(<16 x i64> %v) {207entry:208 %res = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %v)209 ret i64 %res210}211 212declare i8 @llvm.vector.reduce.and.v2i8(<2 x i8>)213declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8>)214declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)215declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)216declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)217 218declare i16 @llvm.vector.reduce.and.v2i16(<2 x i16>)219declare i16 @llvm.vector.reduce.and.v3i16(<3 x i16>)220declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)221declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)222declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)223 224declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)225declare i32 @llvm.vector.reduce.and.v3i32(<3 x i32>)226declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)227declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)228declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32>)229 230declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)231declare i64 @llvm.vector.reduce.and.v3i64(<3 x i64>)232declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)233declare i64 @llvm.vector.reduce.and.v8i64(<8 x i64>)234declare i64 @llvm.vector.reduce.and.v16i64(<16 x i64>)235