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1; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}3 4target triple = "spir64-unknown-unknown"5 6; CHECK-DAG: %[[Char:.*]] = OpTypeInt 8 07; CHECK-DAG: %[[CharVec2:.*]] = OpTypeVector %[[Char]] 28; CHECK-DAG: %[[CharVec3:.*]] = OpTypeVector %[[Char]] 39 10; CHECK-DAG: %[[Short:.*]] = OpTypeInt 16 011; CHECK-DAG: %[[ShortVec2:.*]] = OpTypeVector %[[Short]] 212; CHECK-DAG: %[[ShortVec3:.*]] = OpTypeVector %[[Short]] 313 14; CHECK-DAG: %[[Int:.*]] = OpTypeInt 32 015; CHECK-DAG: %[[IntVec2:.*]] = OpTypeVector %[[Int]] 216; CHECK-DAG: %[[IntVec3:.*]] = OpTypeVector %[[Int]] 317 18; CHECK-DAG: %[[Long:.*]] = OpTypeInt 64 019; CHECK-DAG: %[[LongVec2:.*]] = OpTypeVector %[[Long]] 220; CHECK-DAG: %[[LongVec3:.*]] = OpTypeVector %[[Long]] 321 22; CHECK: OpFunction23; CHECK: %[[Shuffle1:.*]] = OpVectorShuffle %[[CharVec2]] %[[#]] %[[#]] 1 0xFFFFFFFF24; CHECK: %[[Added1:.*]] = OpExtInst %[[CharVec2]] %[[#]] s_max %[[#]] %[[#]]25; CHECK: %[[Vec2CharR:.*]] = OpCompositeExtract %[[Char]] %[[Added1]] 026; CHECK: OpReturnValue %[[Vec2CharR]]27; CHECK: OpFunctionEnd28 29; CHECK: OpFunction30; CHECK: %[[ParamVec3Char:.*]] = OpFunctionParameter %[[CharVec3]]31; CHECK: %[[Vec3CharItem0:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 032; CHECK: %[[Vec3CharItem1:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 133; CHECK: %[[Vec3CharItem2:.*]] = OpCompositeExtract %[[Char]] %[[ParamVec3Char]] 234; CHECK: %[[Vec3CharR1:.*]] = OpExtInst %[[Char]] %[[#]] s_max %[[Vec3CharItem0]] %[[Vec3CharItem1]]35; CHECK: %[[Vec3CharR2:.*]] = OpExtInst %[[Char]] %[[#]] s_max %[[Vec3CharR1]] %[[Vec3CharItem2]]36; CHECK: OpReturnValue %[[Vec3CharR2]]37; CHECK: OpFunctionEnd38 39; CHECK: OpFunction40; CHECK: %[[Shuffle1:.*]] = OpVectorShuffle %[[ShortVec2]] %[[#]] %[[#]] 1 0xFFFFFFFF41; CHECK: %[[Added1:.*]] = OpExtInst %[[ShortVec2]] %[[#]] s_max %[[#]] %[[#]]42; CHECK: %[[Vec2ShortR:.*]] = OpCompositeExtract %[[Short]] %[[Added1]] 043; CHECK: OpReturnValue %[[Vec2ShortR]]44; CHECK: OpFunctionEnd45 46; CHECK: OpFunction47; CHECK: %[[ParamVec3Short:.*]] = OpFunctionParameter %[[ShortVec3]]48; CHECK: %[[Vec3ShortItem0:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 049; CHECK: %[[Vec3ShortItem1:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 150; CHECK: %[[Vec3ShortItem2:.*]] = OpCompositeExtract %[[Short]] %[[ParamVec3Short]] 251; CHECK: %[[Vec3ShortR1:.*]] = OpExtInst %[[Short]] %[[#]] s_max %[[Vec3ShortItem0]] %[[Vec3ShortItem1]]52; CHECK: %[[Vec3ShortR2:.*]] = OpExtInst %[[Short]] %[[#]] s_max %[[Vec3ShortR1]] %[[Vec3ShortItem2]]53; CHECK: OpReturnValue %[[Vec3ShortR2]]54; CHECK: OpFunctionEnd55 56; CHECK: OpFunction57; CHECK: %[[Shuffle1:.*]] = OpVectorShuffle %[[IntVec2]] %[[#]] %[[#]] 1 0xFFFFFFFF58; CHECK: %[[Added1:.*]] = OpExtInst %[[IntVec2]] %[[#]] s_max %[[#]] %[[#]]59; CHECK: %[[Vec2IntR:.*]] = OpCompositeExtract %[[Int]] %[[Added1]] 060; CHECK: OpReturnValue %[[Vec2IntR]]61; CHECK: OpFunctionEnd62 63; CHECK: OpFunction64; CHECK: %[[ParamVec3Int:.*]] = OpFunctionParameter %[[IntVec3]]65; CHECK: %[[Vec3IntItem0:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 066; CHECK: %[[Vec3IntItem1:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 167; CHECK: %[[Vec3IntItem2:.*]] = OpCompositeExtract %[[Int]] %[[ParamVec3Int]] 268; CHECK: %[[Vec3IntR1:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec3IntItem0]] %[[Vec3IntItem1]]69; CHECK: %[[Vec3IntR2:.*]] = OpExtInst %[[Int]] %[[#]] s_max %[[Vec3IntR1]] %[[Vec3IntItem2]]70; CHECK: OpReturnValue %[[Vec3IntR2]]71; CHECK: OpFunctionEnd72 73; CHECK: OpFunction74; CHECK: %[[Shuffle1:.*]] = OpVectorShuffle %[[LongVec2]] %[[#]] %[[#]] 1 0xFFFFFFFF75; CHECK: %[[Added1:.*]] = OpExtInst %[[LongVec2]] %[[#]] s_max %[[#]] %[[#]]76; CHECK: %[[Vec2LongR:.*]] = OpCompositeExtract %[[Long]] %[[Added1]] 077; CHECK: OpReturnValue %[[Vec2LongR]]78; CHECK: OpFunctionEnd79 80; CHECK: OpFunction81; CHECK: %[[ParamVec3Long:.*]] = OpFunctionParameter %[[LongVec3]]82; CHECK: %[[Vec3LongItem0:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 083; CHECK: %[[Vec3LongItem1:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 184; CHECK: %[[Vec3LongItem2:.*]] = OpCompositeExtract %[[Long]] %[[ParamVec3Long]] 285; CHECK: %[[Vec3LongR1:.*]] = OpExtInst %[[Long]] %[[#]] s_max %[[Vec3LongItem0]] %[[Vec3LongItem1]]86; CHECK: %[[Vec3LongR2:.*]] = OpExtInst %[[Long]] %[[#]] s_max %[[Vec3LongR1]] %[[Vec3LongItem2]]87; CHECK: OpReturnValue %[[Vec3LongR2]]88; CHECK: OpFunctionEnd89 90define spir_func i8 @test_vector_reduce_smax_v2i8(<2 x i8> %v) {91entry:92 %res = call i8 @llvm.vector.reduce.smax.v2i8(<2 x i8> %v)93 ret i8 %res94}95 96define spir_func i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) {97entry:98 %res = call i8 @llvm.vector.reduce.smax.v3i8(<3 x i8> %v)99 ret i8 %res100}101 102define spir_func i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {103entry:104 %res = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> %v)105 ret i8 %res106}107 108define spir_func i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {109entry:110 %res = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %v)111 ret i8 %res112}113 114define spir_func i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {115entry:116 %res = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %v)117 ret i8 %res118}119 120define spir_func i16 @test_vector_reduce_smax_v2i16(<2 x i16> %v) {121entry:122 %res = call i16 @llvm.vector.reduce.smax.v2i16(<2 x i16> %v)123 ret i16 %res124}125 126define spir_func i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {127entry:128 %res = call i16 @llvm.vector.reduce.smax.v3i16(<3 x i16> %v)129 ret i16 %res130}131 132define spir_func i16 @test_vector_reduce_smax_v4i16(<4 x i16> %v) {133entry:134 %res = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %v)135 ret i16 %res136}137 138define spir_func i16 @test_vector_reduce_smax_v8i16(<8 x i16> %v) {139entry:140 %res = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %v)141 ret i16 %res142}143 144define spir_func i16 @test_vector_reduce_smax_v16i16(<16 x i16> %v) {145entry:146 %res = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %v)147 ret i16 %res148}149 150 151define spir_func i32 @test_vector_reduce_smax_v2i32(<2 x i32> %v) {152entry:153 %res = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %v)154 ret i32 %res155}156 157define spir_func i32 @test_vector_reduce_smax_v3i32(<3 x i32> %v) {158entry:159 %res = call i32 @llvm.vector.reduce.smax.v3i32(<3 x i32> %v)160 ret i32 %res161}162 163define spir_func i32 @test_vector_reduce_smax_v4i32(<4 x i32> %v) {164entry:165 %res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %v)166 ret i32 %res167}168 169define spir_func i32 @test_vector_reduce_smax_v8i32(<8 x i32> %v) {170entry:171 %res = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v)172 ret i32 %res173}174 175define spir_func i32 @test_vector_reduce_smax_v16i32(<16 x i32> %v) {176entry:177 %res = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %v)178 ret i32 %res179}180 181define spir_func i64 @test_vector_reduce_smax_v2i64(<2 x i64> %v) {182entry:183 %res = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %v)184 ret i64 %res185}186 187define spir_func i64 @test_vector_reduce_smax_v3i64(<3 x i64> %v) {188entry:189 %res = call i64 @llvm.vector.reduce.smax.v3i64(<3 x i64> %v)190 ret i64 %res191}192 193define spir_func i64 @test_vector_reduce_smax_v4i64(<4 x i64> %v) {194entry:195 %res = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)196 ret i64 %res197}198 199define spir_func i64 @test_vector_reduce_smax_v8i64(<8 x i64> %v) {200entry:201 %res = call i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %v)202 ret i64 %res203}204 205define spir_func i64 @test_vector_reduce_smax_v16i64(<16 x i64> %v) {206entry:207 %res = call i64 @llvm.vector.reduce.smax.v16i64(<16 x i64> %v)208 ret i64 %res209}210 211declare i8 @llvm.vector.reduce.smax.v2i8(<2 x i8>)212declare i8 @llvm.vector.reduce.smax.v3i8(<3 x i8>)213declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)214declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)215declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>)216 217declare i16 @llvm.vector.reduce.smax.v2i16(<2 x i16>)218declare i16 @llvm.vector.reduce.smax.v3i16(<3 x i16>)219declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>)220declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>)221declare i16 @llvm.vector.reduce.smax.v16i16(<16 x i16>)222 223declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>)224declare i32 @llvm.vector.reduce.smax.v3i32(<3 x i32>)225declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)226declare i32 @llvm.vector.reduce.smax.v8i32(<8 x i32>)227declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)228 229declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)230declare i64 @llvm.vector.reduce.smax.v3i64(<3 x i64>)231declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>)232declare i64 @llvm.vector.reduce.smax.v8i64(<8 x i64>)233declare i64 @llvm.vector.reduce.smax.v16i64(<16 x i64>)234