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1; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s2; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s3; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}4; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}5 6; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "OpenCL.std"7 8; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 649; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 3210; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 1611 12; CHECK-DAG: %[[#int_64:]] = OpTypeInt 6413; CHECK-DAG: %[[#int_32:]] = OpTypeInt 3214; CHECK-DAG: %[[#int_16:]] = OpTypeInt 1615 16; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 417; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 418; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 419 20; CHECK-DAG: %[[#vec4_int_64:]] = OpTypeVector %[[#int_64]] 421; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 422; CHECK-DAG: %[[#vec4_int_16:]] = OpTypeVector %[[#int_16]] 423 24; CHECK-LABEL: Begin function test_sclamp_i1625define noundef i16 @test_sclamp_i16(i16 noundef %a, i16 noundef %b, i16 noundef %c) {26entry:27 ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]28 ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]29 ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]30 ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] s_clamp %[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]31 %0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c)32 ret i16 %033}34 35; CHECK-LABEL: Begin function test_sclamp_i3236define noundef i32 @test_sclamp_i32(i32 noundef %a, i32 noundef %b, i32 noundef %c) {37entry:38 ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]39 ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]40 ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]41 ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] s_clamp %[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]42 %0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c)43 ret i32 %044}45 46; CHECK-LABEL: Begin function test_sclamp_i6447define noundef i64 @test_sclamp_i64(i64 noundef %a, i64 noundef %b, i64 noundef %c) {48entry:49 ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]50 ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]51 ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]52 ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] s_clamp %[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]53 %0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c)54 ret i64 %055}56 57; CHECK-LABEL: Begin function test_nclamp_half58define noundef half @test_nclamp_half(half noundef %a, half noundef %b, half noundef %c) {59entry:60 ; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]61 ; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]62 ; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]63 ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] fclamp %[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]64 %0 = call half @llvm.spv.nclamp.f16(half %a, half %b, half %c)65 ret half %066}67 68; CHECK-LABEL: Begin function test_nclamp_float69define noundef float @test_nclamp_float(float noundef %a, float noundef %b, float noundef %c) {70entry:71 ; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]72 ; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]73 ; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]74 ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] fclamp %[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]75 %0 = call float @llvm.spv.nclamp.f32(float %a, float %b, float %c)76 ret float %077}78 79; CHECK-LABEL: Begin function test_nclamp_double80define noundef double @test_nclamp_double(double noundef %a, double noundef %b, double noundef %c) {81entry:82 ; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]83 ; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]84 ; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]85 ; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] fclamp %[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]86 %0 = call double @llvm.spv.nclamp.f64(double %a, double %b, double %c)87 ret double %088}89 90; CHECK-LABEL: Begin function test_uclamp_i1691define noundef i16 @test_uclamp_i16(i16 noundef %a, i16 noundef %b, i16 noundef %c) {92entry:93 ; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]94 ; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]95 ; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]96 ; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] u_clamp %[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]97 %0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c)98 ret i16 %099}100 101; CHECK-LABEL: Begin function test_uclamp_i32102define noundef i32 @test_uclamp_i32(i32 noundef %a, i32 noundef %b, i32 noundef %c) {103entry:104 ; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]105 ; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]106 ; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]107 ; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] u_clamp %[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]108 %0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c)109 ret i32 %0110}111 112; CHECK-LABEL: Begin function test_uclamp_i64113define noundef i64 @test_uclamp_i64(i64 noundef %a, i64 noundef %b, i64 noundef %c) {114entry:115 ; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]116 ; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]117 ; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]118 ; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] u_clamp %[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]119 %0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c)120 ret i64 %0121}122 123declare half @llvm.spv.nclamp.f16(half, half, half)124declare float @llvm.spv.nclamp.f32(float, float, float)125declare double @llvm.spv.nclamp.f64(double, double, double)126declare i16 @llvm.spv.sclamp.i16(i16, i16, i16)127declare i32 @llvm.spv.sclamp.i32(i32, i32, i32)128declare i64 @llvm.spv.sclamp.i64(i64, i64, i64)129declare i16 @llvm.spv.uclamp.i16(i16, i16, i16)130declare i32 @llvm.spv.uclamp.i32(i32, i32, i32)131declare i64 @llvm.spv.uclamp.i64(i64, i64, i64)132 133; CHECK-LABEL: Begin function test_sclamp_v4i16134define noundef <4 x i16> @test_sclamp_v4i16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) {135entry:136 ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]137 ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]138 ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]139 ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] s_clamp %[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]140 %0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c)141 ret <4 x i16> %0142}143 144; CHECK-LABEL: Begin function test_sclamp_v4i32145define noundef <4 x i32> @test_sclamp_v4i32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) {146entry:147 ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]148 ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]149 ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]150 ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] s_clamp %[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]151 %0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)152 ret <4 x i32> %0153}154 155; CHECK-LABEL: Begin function test_sclamp_v4i64156define noundef <4 x i64> @test_sclamp_v4i64(<4 x i64> noundef %a, <4 x i64> noundef %b, <4 x i64> noundef %c) {157entry:158 ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]159 ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]160 ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]161 ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] s_clamp %[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]162 %0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c)163 ret <4 x i64> %0164}165 166; CHECK-LABEL: Begin function test_nclamp_v4half167define noundef <4 x half> @test_nclamp_v4half(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) {168entry:169 ; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]170 ; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]171 ; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]172 ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] fclamp %[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]173 %0 = call <4 x half> @llvm.spv.nclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)174 ret <4 x half> %0175}176 177; CHECK-LABEL: Begin function test_nclamp_v4float178define noundef <4 x float> @test_nclamp_v4float(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) {179entry:180 ; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]181 ; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]182 ; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]183 ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] fclamp %[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]184 %0 = call <4 x float> @llvm.spv.nclamp.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)185 ret <4 x float> %0186}187 188; CHECK-LABEL: Begin function test_nclamp_v4double189define noundef <4 x double> @test_nclamp_v4double(<4 x double> noundef %a, <4 x double> noundef %b, <4 x double> noundef %c) {190entry:191 ; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]192 ; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]193 ; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]194 ; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] fclamp %[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]195 %0 = call <4 x double> @llvm.spv.nclamp.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c)196 ret <4 x double> %0197}198 199; CHECK-LABEL: Begin function test_uclamp_v4i16200define noundef <4 x i16> @test_uclamp_v4i16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) {201entry:202 ; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]203 ; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]204 ; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]205 ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] u_clamp %[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]206 %0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c)207 ret <4 x i16> %0208}209 210; CHECK-LABEL: Begin function test_uclamp_v4i32211define noundef <4 x i32> @test_uclamp_v4i32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) {212entry:213 ; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]214 ; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]215 ; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]216 ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] u_clamp %[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]217 %0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)218 ret <4 x i32> %0219}220 221; CHECK-LABEL: Begin function test_uclamp_v4i64222define noundef <4 x i64> @test_uclamp_v4i64(<4 x i64> noundef %a, <4 x i64> noundef %b, <4 x i64> noundef %c) {223entry:224 ; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]225 ; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]226 ; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]227 ; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] u_clamp %[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]228 %0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c)229 ret <4 x i64> %0230}231 232declare <4 x half> @llvm.spv.nclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)233declare <4 x float> @llvm.spv.nclamp.v4f32(<4 x float>, <4 x float>, <4 x float>)234declare <4 x double> @llvm.spv.nclamp.v4f64(<4 x double>, <4 x double>, <4 x double>)235declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)236declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)237declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)238declare <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)239declare <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)240declare <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)241 242 243