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1; RUN: llc -O0 -mtriple=spirv-unknown-vulkan %s -o - | FileCheck %s2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan %s -o - -filetype=obj | spirv-val %}3 4 5define spir_func noundef i32 @test_branch(i32 noundef %X) {6entry:7; CHECK-LABEL: ; -- Begin function test_branch8; CHECK: OpSelectionMerge %[[#]] DontFlatten9 %X.addr = alloca i32, align 410 %resp = alloca i32, align 411 store i32 %X, ptr %X.addr, align 412 %0 = load i32, ptr %X.addr, align 413 %cmp = icmp sgt i32 %0, 014 br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !015 16if.then: ; preds = %entry17 %1 = load i32, ptr %X.addr, align 418 %sub = sub nsw i32 0, %119 store i32 %sub, ptr %resp, align 420 br label %if.end21 22if.else: ; preds = %entry23 %2 = load i32, ptr %X.addr, align 424 %mul = mul nsw i32 %2, 225 store i32 %mul, ptr %resp, align 426 br label %if.end27 28if.end: ; preds = %if.else, %if.then29 %3 = load i32, ptr %resp, align 430 ret i32 %331}32 33 34define spir_func noundef i32 @test_flatten(i32 noundef %X) {35entry:36; CHECK-LABEL: ; -- Begin function test_flatten37; CHECK: OpSelectionMerge %[[#]] Flatten38 %X.addr = alloca i32, align 439 %resp = alloca i32, align 440 store i32 %X, ptr %X.addr, align 441 %0 = load i32, ptr %X.addr, align 442 %cmp = icmp sgt i32 %0, 043 br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !144 45if.then: ; preds = %entry46 %1 = load i32, ptr %X.addr, align 447 %sub = sub nsw i32 0, %148 store i32 %sub, ptr %resp, align 449 br label %if.end50 51if.else: ; preds = %entry52 %2 = load i32, ptr %X.addr, align 453 %mul = mul nsw i32 %2, 254 store i32 %mul, ptr %resp, align 455 br label %if.end56 57if.end: ; preds = %if.else, %if.then58 %3 = load i32, ptr %resp, align 459 ret i32 %360}61 62define spir_func noundef i32 @test_no_attr(i32 noundef %X) {63entry:64; CHECK-LABEL: ; -- Begin function test_no_attr65; CHECK: OpSelectionMerge %[[#]] None66 %X.addr = alloca i32, align 467 %resp = alloca i32, align 468 store i32 %X, ptr %X.addr, align 469 %0 = load i32, ptr %X.addr, align 470 %cmp = icmp sgt i32 %0, 071 br i1 %cmp, label %if.then, label %if.else72 73if.then: ; preds = %entry74 %1 = load i32, ptr %X.addr, align 475 %sub = sub nsw i32 0, %176 store i32 %sub, ptr %resp, align 477 br label %if.end78 79if.else: ; preds = %entry80 %2 = load i32, ptr %X.addr, align 481 %mul = mul nsw i32 %2, 282 store i32 %mul, ptr %resp, align 483 br label %if.end84 85if.end: ; preds = %if.else, %if.then86 %3 = load i32, ptr %resp, align 487 ret i32 %388}89 90define spir_func noundef i32 @flatten_switch(i32 noundef %X) {91entry:92; CHECK-LABEL: ; -- Begin function flatten_switch93; CHECK: OpSelectionMerge %[[#]] Flatten94 %X.addr = alloca i32, align 495 %resp = alloca i32, align 496 store i32 %X, ptr %X.addr, align 497 %0 = load i32, ptr %X.addr, align 498 switch i32 %0, label %sw.epilog [99 i32 0, label %sw.bb100 i32 1, label %sw.bb1101 i32 2, label %sw.bb2102 ], !hlsl.controlflow.hint !1103 104sw.bb: ; preds = %entry105 %1 = load i32, ptr %X.addr, align 4106 %sub = sub nsw i32 0, %1107 store i32 %sub, ptr %resp, align 4108 br label %sw.epilog109 110sw.bb1: ; preds = %entry111 %2 = load i32, ptr %X.addr, align 4112 %3 = load i32, ptr %X.addr, align 4113 %add = add nsw i32 %2, %3114 store i32 %add, ptr %resp, align 4115 br label %sw.epilog116 117sw.bb2: ; preds = %entry118 %4 = load i32, ptr %X.addr, align 4119 %5 = load i32, ptr %X.addr, align 4120 %mul = mul nsw i32 %4, %5121 store i32 %mul, ptr %resp, align 4122 br label %sw.epilog123 124sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb125 %6 = load i32, ptr %resp, align 4126 ret i32 %6127}128 129 130define spir_func noundef i32 @branch_switch(i32 noundef %X) {131 entry:132 ; CHECK-LABEL: ; -- Begin function branch_switch133 ; CHECK: OpSelectionMerge %[[#]] DontFlatten134 %X.addr = alloca i32, align 4135 %resp = alloca i32, align 4136 store i32 %X, ptr %X.addr, align 4137 %0 = load i32, ptr %X.addr, align 4138 switch i32 %0, label %sw.epilog [139 i32 0, label %sw.bb140 i32 1, label %sw.bb1141 i32 2, label %sw.bb2142 ], !hlsl.controlflow.hint !0143 144sw.bb: ; preds = %entry145 %1 = load i32, ptr %X.addr, align 4146 %sub = sub nsw i32 0, %1147 store i32 %sub, ptr %resp, align 4148 br label %sw.epilog149 150sw.bb1: ; preds = %entry151 %2 = load i32, ptr %X.addr, align 4152 %3 = load i32, ptr %X.addr, align 4153 %add = add nsw i32 %2, %3154 store i32 %add, ptr %resp, align 4155 br label %sw.epilog156 157sw.bb2: ; preds = %entry158 %4 = load i32, ptr %X.addr, align 4159 %5 = load i32, ptr %X.addr, align 4160 %mul = mul nsw i32 %4, %5161 store i32 %mul, ptr %resp, align 4162 br label %sw.epilog163 164sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb165 %6 = load i32, ptr %resp, align 4166 ret i32 %6167}168 169 170define spir_func noundef i32 @no_attr_switch(i32 noundef %X) {171 ; CHECK-LABEL: ; -- Begin function no_attr_switch172; CHECK: OpSelectionMerge %[[#]] None173entry:174 %X.addr = alloca i32, align 4175 %resp = alloca i32, align 4176 store i32 %X, ptr %X.addr, align 4177 %0 = load i32, ptr %X.addr, align 4178 switch i32 %0, label %sw.epilog [179 i32 0, label %sw.bb180 i32 1, label %sw.bb1181 i32 2, label %sw.bb2182 ]183 184sw.bb: ; preds = %entry185 %1 = load i32, ptr %X.addr, align 4186 %sub = sub nsw i32 0, %1187 store i32 %sub, ptr %resp, align 4188 br label %sw.epilog189 190sw.bb1: ; preds = %entry191 %2 = load i32, ptr %X.addr, align 4192 %3 = load i32, ptr %X.addr, align 4193 %add = add nsw i32 %2, %3194 store i32 %add, ptr %resp, align 4195 br label %sw.epilog196 197sw.bb2: ; preds = %entry198 %4 = load i32, ptr %X.addr, align 4199 %5 = load i32, ptr %X.addr, align 4200 %mul = mul nsw i32 %4, %5201 store i32 %mul, ptr %resp, align 4202 br label %sw.epilog203 204sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb205 %6 = load i32, ptr %resp, align 4206 ret i32 %6207}208 209!0 = !{!"hlsl.controlflow.hint", i32 1}210!1 = !{!"hlsl.controlflow.hint", i32 2}211