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1; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}3 4;5; int foo() { return 200; }6;7; int process() {8; int a = 0;9; int b = 0;10; int c = 0;11; const int r = 20;12; const int s = 40;13; const int t = 3*r+2*s;14;15;16; ////////////////////////////////////////17; // DefaultStmt is the first statement //18; ////////////////////////////////////////19; switch(a) {20; default:21; b += 0;22; case 1:23; b += 1;24; break;25; case 2:26; b += 2;27; }28;29;30; //////////////////////////////////////////////31; // DefaultStmt in the middle of other cases //32; //////////////////////////////////////////////33; switch(a) {34; case 10:35; b += 1;36; default:37; b += 0;38; case 20:39; b += 2;40; break;41; }42;43; ///////////////////////////////////////////////44; // Various CaseStmt and BreakStmt topologies //45; // DefaultStmt is the last statement //46; ///////////////////////////////////////////////47; switch(int d = 5) {48; case 1:49; b += 1;50; c += foo();51; case 2:52; b += 2;53; break;54; case 3:55; {56; b += 3;57; break;58; }59; case t:60; b += t;61; case 4:62; case 5:63; b += 5;64; break;65; case 6: {66; case 7:67; break;}68; default:69; break;70; }71;72;73; //////////////////////////74; // No Default statement //75; //////////////////////////76; switch(a) {77; case 100:78; b += 100;79; break;80; }81;82;83; /////////////////////////////////////////////////////////84; // No cases. Only a default //85; // This means the default body will always be executed //86; /////////////////////////////////////////////////////////87; switch(a) {88; default:89; b += 100;90; c += 200;91; break;92; }93;94;95; ////////////////////////////////////////////////////////////96; // Nested Switch with branching //97; // The two inner switch statements should be executed for //98; // both cases of the outer switch (case 300 and case 400) //99; ////////////////////////////////////////////////////////////100; switch(a) {101; case 300:102; b += 300;103; case 400:104; switch(c) {105; case 500:106; b += 500;107; break;108; case 600:109; switch(b) {110; default:111; a += 600;112; b += 600;113; }114; }115; }116;117; return a + b + c;118; }119;120; [numthreads(1, 1, 1)]121; void main() {122; process();123; }124 125; CHECK: %[[#func_22:]] = OpFunction %[[#uint:]] DontInline %[[#]]126; CHECK: %[[#bb94:]] = OpLabel127; CHECK: OpReturnValue %[[#]]128; CHECK: OpFunctionEnd129; CHECK: %[[#func_23:]] = OpFunction %[[#uint:]] DontInline %[[#]]130; CHECK: %[[#bb95:]] = OpLabel131; CHECK: OpSelectionMerge %[[#bb96:]] None132; CHECK: OpBranchConditional %[[#]] %[[#bb97:]] %[[#bb98:]]133; CHECK: %[[#bb97:]] = OpLabel134; CHECK: OpSelectionMerge %[[#bb99:]] None135; CHECK: OpSwitch %[[#]] %[[#bb100:]] 1 %[[#bb99:]] 2 %[[#bb101:]]136; CHECK: %[[#bb98:]] = OpLabel137; CHECK: %[[#bb100:]] = OpLabel138; CHECK: OpBranch %[[#bb99:]]139; CHECK: %[[#bb101:]] = OpLabel140; CHECK: OpBranch %[[#bb99:]]141; CHECK: %[[#bb99:]] = OpLabel142; CHECK: OpBranchConditional %[[#]] %[[#bb102:]] %[[#bb96:]]143; CHECK: %[[#bb102:]] = OpLabel144; CHECK: OpBranch %[[#bb96:]]145; CHECK: %[[#bb96:]] = OpLabel146; CHECK: OpSelectionMerge %[[#bb103:]] None147; CHECK: OpBranchConditional %[[#]] %[[#bb104:]] %[[#bb105:]]148; CHECK: %[[#bb104:]] = OpLabel149; CHECK: OpSelectionMerge %[[#bb106:]] None150; CHECK: OpSwitch %[[#]] %[[#bb106:]] 10 %[[#bb107:]] 20 %[[#bb108:]]151; CHECK: %[[#bb105:]] = OpLabel152; CHECK: %[[#bb107:]] = OpLabel153; CHECK: OpBranch %[[#bb106:]]154; CHECK: %[[#bb108:]] = OpLabel155; CHECK: OpBranch %[[#bb106:]]156; CHECK: %[[#bb106:]] = OpLabel157; CHECK: OpBranchConditional %[[#]] %[[#bb109:]] %[[#bb103:]]158; CHECK: %[[#bb109:]] = OpLabel159; CHECK: OpBranch %[[#bb103:]]160; CHECK: %[[#bb103:]] = OpLabel161; CHECK: OpBranch %[[#bb110:]]162; CHECK: %[[#bb110:]] = OpLabel163; CHECK: OpSelectionMerge %[[#bb111:]] None164; CHECK: OpBranchConditional %[[#]] %[[#bb112:]] %[[#bb113:]]165; CHECK: %[[#bb112:]] = OpLabel166; CHECK: OpSelectionMerge %[[#bb114:]] None167; CHECK: OpBranchConditional %[[#]] %[[#bb115:]] %[[#bb116:]]168; CHECK: %[[#bb113:]] = OpLabel169; CHECK: %[[#bb115:]] = OpLabel170; CHECK: OpSelectionMerge %[[#bb117:]] None171; CHECK: OpBranchConditional %[[#]] %[[#bb118:]] %[[#bb119:]]172; CHECK: %[[#bb116:]] = OpLabel173; CHECK: %[[#bb118:]] = OpLabel174; CHECK: OpSelectionMerge %[[#bb120:]] None175; CHECK: OpSwitch %[[#]] %[[#bb121:]] 1 %[[#bb122:]] 2 %[[#bb120:]] 3 %[[#bb123:]] 140 %[[#bb124:]] 4 %[[#bb125:]] 5 %[[#bb126:]] 6 %[[#bb127:]] 7 %[[#bb128:]]176; CHECK: %[[#bb119:]] = OpLabel177; CHECK: %[[#bb121:]] = OpLabel178; CHECK: OpBranch %[[#bb120:]]179; CHECK: %[[#bb122:]] = OpLabel180; CHECK: OpBranch %[[#bb120:]]181; CHECK: %[[#bb123:]] = OpLabel182; CHECK: OpBranch %[[#bb120:]]183; CHECK: %[[#bb124:]] = OpLabel184; CHECK: OpBranch %[[#bb120:]]185; CHECK: %[[#bb125:]] = OpLabel186; CHECK: OpBranch %[[#bb120:]]187; CHECK: %[[#bb126:]] = OpLabel188; CHECK: OpBranch %[[#bb120:]]189; CHECK: %[[#bb127:]] = OpLabel190; CHECK: OpBranch %[[#bb120:]]191; CHECK: %[[#bb128:]] = OpLabel192; CHECK: OpBranch %[[#bb120:]]193; CHECK: %[[#bb120:]] = OpLabel194; CHECK: OpSelectionMerge %[[#bb129:]] None195; CHECK: OpSwitch %[[#]] %[[#bb130:]] 1 %[[#bb129:]] 2 %[[#bb131:]] 3 %[[#bb132:]]196; CHECK: %[[#bb130:]] = OpLabel197; CHECK: OpBranch %[[#bb129:]]198; CHECK: %[[#bb131:]] = OpLabel199; CHECK: OpBranch %[[#bb129:]]200; CHECK: %[[#bb132:]] = OpLabel201; CHECK: OpBranch %[[#bb129:]]202; CHECK: %[[#bb129:]] = OpLabel203; CHECK: OpBranch %[[#bb117:]]204; CHECK: %[[#bb117:]] = OpLabel205; CHECK: OpSelectionMerge %[[#bb133:]] None206; CHECK: OpSwitch %[[#]] %[[#bb134:]] 1 %[[#bb133:]] 2 %[[#bb135:]]207; CHECK: %[[#bb134:]] = OpLabel208; CHECK: OpBranch %[[#bb133:]]209; CHECK: %[[#bb135:]] = OpLabel210; CHECK: OpBranch %[[#bb133:]]211; CHECK: %[[#bb133:]] = OpLabel212; CHECK: OpBranch %[[#bb114:]]213; CHECK: %[[#bb114:]] = OpLabel214; CHECK: OpBranch %[[#bb111:]]215; CHECK: %[[#bb111:]] = OpLabel216; CHECK: OpSelectionMerge %[[#bb136:]] None217; CHECK: OpBranchConditional %[[#]] %[[#bb137:]] %[[#bb136:]]218; CHECK: %[[#bb137:]] = OpLabel219; CHECK: OpBranch %[[#bb136:]]220; CHECK: %[[#bb136:]] = OpLabel221; CHECK: OpBranch %[[#bb138:]]222; CHECK: %[[#bb138:]] = OpLabel223; CHECK: OpBranch %[[#bb139:]]224; CHECK: %[[#bb139:]] = OpLabel225; CHECK: OpSelectionMerge %[[#bb140:]] None226; CHECK: OpBranchConditional %[[#]] %[[#bb141:]] %[[#bb142:]]227; CHECK: %[[#bb141:]] = OpLabel228; CHECK: OpSelectionMerge %[[#bb143:]] None229; CHECK: OpSwitch %[[#]] %[[#bb143:]] 300 %[[#bb144:]] 400 %[[#bb145:]]230; CHECK: %[[#bb142:]] = OpLabel231; CHECK: %[[#bb144:]] = OpLabel232; CHECK: OpBranch %[[#bb143:]]233; CHECK: %[[#bb145:]] = OpLabel234; CHECK: OpBranch %[[#bb143:]]235; CHECK: %[[#bb143:]] = OpLabel236; CHECK: OpBranchConditional %[[#]] %[[#bb140:]] %[[#bb146:]]237; CHECK: %[[#bb146:]] = OpLabel238; CHECK: OpSelectionMerge %[[#bb147:]] None239; CHECK: OpSwitch %[[#]] %[[#bb147:]] 500 %[[#bb148:]] 600 %[[#bb149:]]240; CHECK: %[[#bb148:]] = OpLabel241; CHECK: OpBranch %[[#bb147:]]242; CHECK: %[[#bb149:]] = OpLabel243; CHECK: OpBranch %[[#bb150:]]244; CHECK: %[[#bb150:]] = OpLabel245; CHECK: OpBranch %[[#bb147:]]246; CHECK: %[[#bb147:]] = OpLabel247; CHECK: OpBranch %[[#bb140:]]248; CHECK: %[[#bb140:]] = OpLabel249; CHECK: OpReturnValue %[[#]]250; CHECK: OpFunctionEnd251; CHECK: %[[#func_90:]] = OpFunction %[[#void:]] DontInline %[[#]]252; CHECK: %[[#bb151:]] = OpLabel253; CHECK: OpReturn254; CHECK: OpFunctionEnd255; CHECK: %[[#func_92:]] = OpFunction %[[#void:]] None %[[#]]256; CHECK: %[[#bb152:]] = OpLabel257; CHECK: OpReturn258; CHECK: OpFunctionEnd259 260 261 262target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"263target triple = "spirv-unknown-vulkan1.3-compute"264 265; Function Attrs: convergent noinline norecurse nounwind optnone266define spir_func noundef i32 @_Z3foov() #0 {267entry:268 %0 = call token @llvm.experimental.convergence.entry()269 ret i32 200270}271 272; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)273declare token @llvm.experimental.convergence.entry() #1274 275; Function Attrs: convergent noinline norecurse nounwind optnone276define spir_func noundef i32 @_Z7processv() #0 {277entry:278 %0 = call token @llvm.experimental.convergence.entry()279 %a = alloca i32, align 4280 %b = alloca i32, align 4281 %c = alloca i32, align 4282 %r = alloca i32, align 4283 %s = alloca i32, align 4284 %t = alloca i32, align 4285 %d = alloca i32, align 4286 store i32 0, ptr %a, align 4287 store i32 0, ptr %b, align 4288 store i32 0, ptr %c, align 4289 store i32 20, ptr %r, align 4290 store i32 40, ptr %s, align 4291 store i32 140, ptr %t, align 4292 %1 = load i32, ptr %a, align 4293 switch i32 %1, label %sw.default [294 i32 1, label %sw.bb295 i32 2, label %sw.bb2296 ]297 298sw.default: ; preds = %entry299 %2 = load i32, ptr %b, align 4300 %add = add nsw i32 %2, 0301 store i32 %add, ptr %b, align 4302 br label %sw.bb303 304sw.bb: ; preds = %entry, %sw.default305 %3 = load i32, ptr %b, align 4306 %add1 = add nsw i32 %3, 1307 store i32 %add1, ptr %b, align 4308 br label %sw.epilog309 310sw.bb2: ; preds = %entry311 %4 = load i32, ptr %b, align 4312 %add3 = add nsw i32 %4, 2313 store i32 %add3, ptr %b, align 4314 br label %sw.epilog315 316sw.epilog: ; preds = %sw.bb2, %sw.bb317 %5 = load i32, ptr %a, align 4318 switch i32 %5, label %sw.default6 [319 i32 10, label %sw.bb4320 i32 20, label %sw.bb8321 ]322 323sw.bb4: ; preds = %sw.epilog324 %6 = load i32, ptr %b, align 4325 %add5 = add nsw i32 %6, 1326 store i32 %add5, ptr %b, align 4327 br label %sw.default6328 329sw.default6: ; preds = %sw.epilog, %sw.bb4330 %7 = load i32, ptr %b, align 4331 %add7 = add nsw i32 %7, 0332 store i32 %add7, ptr %b, align 4333 br label %sw.bb8334 335sw.bb8: ; preds = %sw.epilog, %sw.default6336 %8 = load i32, ptr %b, align 4337 %add9 = add nsw i32 %8, 2338 store i32 %add9, ptr %b, align 4339 br label %sw.epilog10340 341sw.epilog10: ; preds = %sw.bb8342 store i32 5, ptr %d, align 4343 %9 = load i32, ptr %d, align 4344 switch i32 %9, label %sw.default25 [345 i32 1, label %sw.bb11346 i32 2, label %sw.bb15347 i32 3, label %sw.bb17348 i32 140, label %sw.bb19349 i32 4, label %sw.bb21350 i32 5, label %sw.bb21351 i32 6, label %sw.bb23352 i32 7, label %sw.bb24353 ]354 355sw.bb11: ; preds = %sw.epilog10356 %10 = load i32, ptr %b, align 4357 %add12 = add nsw i32 %10, 1358 store i32 %add12, ptr %b, align 4359 %call13 = call spir_func noundef i32 @_Z3foov() #3 [ "convergencectrl"(token %0) ]360 %11 = load i32, ptr %c, align 4361 %add14 = add nsw i32 %11, %call13362 store i32 %add14, ptr %c, align 4363 br label %sw.bb15364 365sw.bb15: ; preds = %sw.epilog10, %sw.bb11366 %12 = load i32, ptr %b, align 4367 %add16 = add nsw i32 %12, 2368 store i32 %add16, ptr %b, align 4369 br label %sw.epilog26370 371sw.bb17: ; preds = %sw.epilog10372 %13 = load i32, ptr %b, align 4373 %add18 = add nsw i32 %13, 3374 store i32 %add18, ptr %b, align 4375 br label %sw.epilog26376 377sw.bb19: ; preds = %sw.epilog10378 %14 = load i32, ptr %b, align 4379 %add20 = add nsw i32 %14, 140380 store i32 %add20, ptr %b, align 4381 br label %sw.bb21382 383sw.bb21: ; preds = %sw.epilog10, %sw.epilog10, %sw.bb19384 %15 = load i32, ptr %b, align 4385 %add22 = add nsw i32 %15, 5386 store i32 %add22, ptr %b, align 4387 br label %sw.epilog26388 389sw.bb23: ; preds = %sw.epilog10390 br label %sw.bb24391 392sw.bb24: ; preds = %sw.epilog10, %sw.bb23393 br label %sw.epilog26394 395sw.default25: ; preds = %sw.epilog10396 br label %sw.epilog26397 398sw.epilog26: ; preds = %sw.default25, %sw.bb24, %sw.bb21, %sw.bb17, %sw.bb15399 %16 = load i32, ptr %a, align 4400 switch i32 %16, label %sw.epilog29 [401 i32 100, label %sw.bb27402 ]403 404sw.bb27: ; preds = %sw.epilog26405 %17 = load i32, ptr %b, align 4406 %add28 = add nsw i32 %17, 100407 store i32 %add28, ptr %b, align 4408 br label %sw.epilog29409 410sw.epilog29: ; preds = %sw.epilog26, %sw.bb27411 %18 = load i32, ptr %a, align 4412 switch i32 %18, label %sw.default30 [413 ]414 415sw.default30: ; preds = %sw.epilog29416 %19 = load i32, ptr %b, align 4417 %add31 = add nsw i32 %19, 100418 store i32 %add31, ptr %b, align 4419 %20 = load i32, ptr %c, align 4420 %add32 = add nsw i32 %20, 200421 store i32 %add32, ptr %c, align 4422 br label %sw.epilog33423 424sw.epilog33: ; preds = %sw.default30425 %21 = load i32, ptr %a, align 4426 switch i32 %21, label %sw.epilog45 [427 i32 300, label %sw.bb34428 i32 400, label %sw.bb36429 ]430 431sw.bb34: ; preds = %sw.epilog33432 %22 = load i32, ptr %b, align 4433 %add35 = add nsw i32 %22, 300434 store i32 %add35, ptr %b, align 4435 br label %sw.bb36436 437sw.bb36: ; preds = %sw.epilog33, %sw.bb34438 %23 = load i32, ptr %c, align 4439 switch i32 %23, label %sw.epilog44 [440 i32 500, label %sw.bb37441 i32 600, label %sw.bb39442 ]443 444sw.bb37: ; preds = %sw.bb36445 %24 = load i32, ptr %b, align 4446 %add38 = add nsw i32 %24, 500447 store i32 %add38, ptr %b, align 4448 br label %sw.epilog44449 450sw.bb39: ; preds = %sw.bb36451 %25 = load i32, ptr %b, align 4452 switch i32 %25, label %sw.default40 [453 ]454 455sw.default40: ; preds = %sw.bb39456 %26 = load i32, ptr %a, align 4457 %add41 = add nsw i32 %26, 600458 store i32 %add41, ptr %a, align 4459 %27 = load i32, ptr %b, align 4460 %add42 = add nsw i32 %27, 600461 store i32 %add42, ptr %b, align 4462 br label %sw.epilog43463 464sw.epilog43: ; preds = %sw.default40465 br label %sw.epilog44466 467sw.epilog44: ; preds = %sw.epilog43, %sw.bb36, %sw.bb37468 br label %sw.epilog45469 470sw.epilog45: ; preds = %sw.epilog44, %sw.epilog33471 %28 = load i32, ptr %a, align 4472 %29 = load i32, ptr %b, align 4473 %add46 = add nsw i32 %28, %29474 %30 = load i32, ptr %c, align 4475 %add47 = add nsw i32 %add46, %30476 ret i32 %add47477}478 479; Function Attrs: convergent noinline norecurse nounwind optnone480define internal spir_func void @main() #0 {481entry:482 %0 = call token @llvm.experimental.convergence.entry()483 %call1 = call spir_func noundef i32 @_Z7processv() #3 [ "convergencectrl"(token %0) ]484 ret void485}486 487; Function Attrs: convergent norecurse488define void @main.1() #2 {489entry:490 call void @main()491 ret void492}493 494attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }495attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }496attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }497attributes #3 = { convergent }498 499!llvm.module.flags = !{!0, !1, !2}500 501 502!0 = !{i32 1, !"wchar_size", i32 4}503!1 = !{i32 4, !"dx.disable_optimizations", i32 1}504!2 = !{i32 7, !"frame-pointer", i32 2}505 506 507