718 lines · plain
1; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}3 4;5; int foo() { return 200; }6;7; [numthreads(1, 1, 1)]8; void main() {9; int result;10;11; ////////////////////////////12; // The most basic case //13; // Has a 'default' case //14; // All cases have 'break' //15; ////////////////////////////16; int a = 0;17; switch(a) {18; case -3:19; result = -300;20; break;21; case 0:22; result = 0;23; break;24; case 1:25; result = 100;26; break;27; case 2:28; result = foo();29; break;30; default:31; result = 777;32; break;33; }34;35; ////////////////////////////////////36; // The selector is a statement //37; // Does not have a 'default' case //38; // All cases have 'break' //39; ////////////////////////////////////40;41; switch(int c = a) {42; case -4:43; result = -400;44; break;45; case 4:46; result = 400;47; break;48; }49;50; ///////////////////////////////////51; // All cases are fall-through //52; // The last case is fall-through //53; ///////////////////////////////////54; switch(a) {55; case -5:56; result = -500;57; case 5:58; result = 500;59; }60;61; ///////////////////////////////////////62; // Some cases are fall-through //63; // The last case is not fall-through //64; ///////////////////////////////////////65;66; switch(a) {67; case 6:68; result = 600;69; case 7:70; result = 700;71; case 8:72; result = 800;73; break;74; default:75; result = 777;76; break;77; }78;79; ///////////////////////////////////////80; // Fall-through cases with no body //81; ///////////////////////////////////////82;83; switch(a) {84; case 10:85; case 11:86; default:87; case 12:88; result = 12;89; }90;91; ////////////////////////////////////////////////92; // No-op. Two nested cases and a nested break //93; ////////////////////////////////////////////////94;95; switch(a) {96; case 15:97; case 16:98; break;99; }100;101; ////////////////////////////////////////////////////////////////102; // Using braces (compound statements) in various parts //103; // Using breaks such that each AST configuration is different //104; // Also uses 'forcecase' attribute //105; ////////////////////////////////////////////////////////////////106;107; switch(a) {108; case 20: {109; result = 20;110; break;111; }112; case 21:113; result = 21;114; break;115; case 22:116; case 23:117; break;118; case 24:119; case 25: { result = 25; }120; break;121; case 26:122; case 27: {123; break;124; }125; case 28: {126; result = 28;127; {{break;}}128; }129; case 29: {130; {131; result = 29;132; {break;}133; }134; }135; }136;137; ////////////////////////////////////////////////////////////////////////138; // Nested Switch statements with mixed use of fall-through and braces //139; ////////////////////////////////////////////////////////////////////////140;141; switch(a) {142; case 30: {143; result = 30;144; switch(result) {145; default:146; a = 55;147; case 50:148; a = 50;149; break;150; case 51:151; case 52:152; a = 52;153; case 53:154; a = 53;155; break;156; case 54 : {157; a = 54;158; break;159; }160; }161; }162; }163;164; ///////////////////////////////////////////////165; // Constant integer variables as case values //166; ///////////////////////////////////////////////167;168; const int r = 35;169; const int s = 45;170; const int t = 2*r + s; // evaluates to 115.171;172; switch(a) {173; case r:174; result = r;175; case t:176; result = t;177; break;178; }179;180;181; //////////////////////////////////////////////////////////////////182; // Using float as selector results in multiple casts in the AST //183; //////////////////////////////////////////////////////////////////184; float sel;185; switch ((int)sel) {186; case 0:187; result = 0;188; break;189; }190; }191 192; CHECK: %[[#func_41:]] = OpFunction %[[#uint:]] DontInline %[[#]]193; CHECK: %[[#bb82:]] = OpLabel194; CHECK: OpReturnValue %[[#]]195; CHECK: OpFunctionEnd196; CHECK: %[[#func_42:]] = OpFunction %[[#void:]] DontInline %[[#]]197; CHECK: %[[#bb83:]] = OpLabel198; CHECK: OpSelectionMerge %[[#bb84:]] None199; CHECK: OpSwitch %[[#]] %[[#bb85:]] 4294967293 %[[#bb86:]] 0 %[[#bb87:]] 1 %[[#bb88:]] 2 %[[#bb89:]]200; CHECK: %[[#bb85:]] = OpLabel201; CHECK: OpBranch %[[#bb84:]]202; CHECK: %[[#bb86:]] = OpLabel203; CHECK: OpBranch %[[#bb84:]]204; CHECK: %[[#bb87:]] = OpLabel205; CHECK: OpBranch %[[#bb84:]]206; CHECK: %[[#bb88:]] = OpLabel207; CHECK: OpBranch %[[#bb84:]]208; CHECK: %[[#bb89:]] = OpLabel209; CHECK: OpBranch %[[#bb84:]]210; CHECK: %[[#bb84:]] = OpLabel211; CHECK: OpSelectionMerge %[[#bb90:]] None212; CHECK: OpSwitch %[[#]] %[[#bb90:]] 4294967292 %[[#bb91:]] 4 %[[#bb92:]]213; CHECK: %[[#bb91:]] = OpLabel214; CHECK: OpBranch %[[#bb90:]]215; CHECK: %[[#bb92:]] = OpLabel216; CHECK: OpBranch %[[#bb90:]]217; CHECK: %[[#bb90:]] = OpLabel218; CHECK: OpSelectionMerge %[[#bb93:]] None219; CHECK: OpBranchConditional %[[#]] %[[#bb94:]] %[[#bb95:]]220; CHECK: %[[#bb94:]] = OpLabel221; CHECK: OpSelectionMerge %[[#bb96:]] None222; CHECK: OpSwitch %[[#]] %[[#bb96:]] 4294967291 %[[#bb97:]] 5 %[[#bb98:]]223; CHECK: %[[#bb95:]] = OpLabel224; CHECK: %[[#bb97:]] = OpLabel225; CHECK: OpBranch %[[#bb96:]]226; CHECK: %[[#bb98:]] = OpLabel227; CHECK: OpBranch %[[#bb96:]]228; CHECK: %[[#bb96:]] = OpLabel229; CHECK: OpBranchConditional %[[#]] %[[#bb93:]] %[[#bb99:]]230; CHECK: %[[#bb99:]] = OpLabel231; CHECK: OpBranch %[[#bb93:]]232; CHECK: %[[#bb93:]] = OpLabel233; CHECK: OpSelectionMerge %[[#bb100:]] None234; CHECK: OpBranchConditional %[[#]] %[[#bb101:]] %[[#bb102:]]235; CHECK: %[[#bb101:]] = OpLabel236; CHECK: OpSelectionMerge %[[#bb103:]] None237; CHECK: OpBranchConditional %[[#]] %[[#bb104:]] %[[#bb105:]]238; CHECK: %[[#bb102:]] = OpLabel239; CHECK: %[[#bb104:]] = OpLabel240; CHECK: OpSelectionMerge %[[#bb106:]] None241; CHECK: OpSwitch %[[#]] %[[#bb107:]] 6 %[[#bb108:]] 7 %[[#bb106:]] 8 %[[#bb109:]]242; CHECK: %[[#bb105:]] = OpLabel243; CHECK: %[[#bb107:]] = OpLabel244; CHECK: OpBranch %[[#bb106:]]245; CHECK: %[[#bb108:]] = OpLabel246; CHECK: OpBranch %[[#bb106:]]247; CHECK: %[[#bb109:]] = OpLabel248; CHECK: OpBranch %[[#bb106:]]249; CHECK: %[[#bb106:]] = OpLabel250; CHECK: OpSelectionMerge %[[#bb110:]] None251; CHECK: OpSwitch %[[#]] %[[#bb111:]] 1 %[[#bb110:]] 2 %[[#bb112:]]252; CHECK: %[[#bb111:]] = OpLabel253; CHECK: OpBranch %[[#bb110:]]254; CHECK: %[[#bb112:]] = OpLabel255; CHECK: OpBranch %[[#bb110:]]256; CHECK: %[[#bb110:]] = OpLabel257; CHECK: OpBranch %[[#bb103:]]258; CHECK: %[[#bb103:]] = OpLabel259; CHECK: OpBranchConditional %[[#]] %[[#bb113:]] %[[#bb100:]]260; CHECK: %[[#bb113:]] = OpLabel261; CHECK: OpBranch %[[#bb100:]]262; CHECK: %[[#bb100:]] = OpLabel263; CHECK: OpSelectionMerge %[[#bb114:]] None264; CHECK: OpBranchConditional %[[#]] %[[#bb115:]] %[[#bb116:]]265; CHECK: %[[#bb115:]] = OpLabel266; CHECK: OpSelectionMerge %[[#bb117:]] None267; CHECK: OpBranchConditional %[[#]] %[[#bb118:]] %[[#bb119:]]268; CHECK: %[[#bb116:]] = OpLabel269; CHECK: %[[#bb118:]] = OpLabel270; CHECK: OpSelectionMerge %[[#bb120:]] None271; CHECK: OpSwitch %[[#]] %[[#bb120:]] 10 %[[#bb121:]] 11 %[[#bb122:]] 12 %[[#bb123:]]272; CHECK: %[[#bb119:]] = OpLabel273; CHECK: %[[#bb121:]] = OpLabel274; CHECK: OpBranch %[[#bb120:]]275; CHECK: %[[#bb122:]] = OpLabel276; CHECK: OpBranch %[[#bb120:]]277; CHECK: %[[#bb123:]] = OpLabel278; CHECK: OpBranch %[[#bb120:]]279; CHECK: %[[#bb120:]] = OpLabel280; CHECK: OpSelectionMerge %[[#bb124:]] None281; CHECK: OpSwitch %[[#]] %[[#bb124:]] 1 %[[#bb125:]] 2 %[[#bb126:]]282; CHECK: %[[#bb125:]] = OpLabel283; CHECK: OpBranch %[[#bb124:]]284; CHECK: %[[#bb126:]] = OpLabel285; CHECK: OpBranch %[[#bb124:]]286; CHECK: %[[#bb124:]] = OpLabel287; CHECK: OpBranch %[[#bb117:]]288; CHECK: %[[#bb117:]] = OpLabel289; CHECK: OpBranch %[[#bb114:]]290; CHECK: %[[#bb114:]] = OpLabel291; CHECK: OpBranch %[[#bb127:]]292; CHECK: %[[#bb127:]] = OpLabel293; CHECK: OpSelectionMerge %[[#bb128:]] None294; CHECK: OpBranchConditional %[[#]] %[[#bb129:]] %[[#bb130:]]295; CHECK: %[[#bb129:]] = OpLabel296; CHECK: OpSelectionMerge %[[#bb131:]] None297; CHECK: OpSwitch %[[#]] %[[#bb131:]] 15 %[[#bb132:]] 16 %[[#bb133:]]298; CHECK: %[[#bb130:]] = OpLabel299; CHECK: %[[#bb132:]] = OpLabel300; CHECK: OpBranch %[[#bb131:]]301; CHECK: %[[#bb133:]] = OpLabel302; CHECK: OpBranch %[[#bb131:]]303; CHECK: %[[#bb131:]] = OpLabel304; CHECK: OpBranch %[[#bb128:]]305; CHECK: %[[#bb128:]] = OpLabel306; CHECK: OpSelectionMerge %[[#bb134:]] None307; CHECK: OpBranchConditional %[[#]] %[[#bb135:]] %[[#bb136:]]308; CHECK: %[[#bb135:]] = OpLabel309; CHECK: OpSelectionMerge %[[#bb137:]] None310; CHECK: OpBranchConditional %[[#]] %[[#bb138:]] %[[#bb139:]]311; CHECK: %[[#bb136:]] = OpLabel312; CHECK: %[[#bb138:]] = OpLabel313; CHECK: OpSelectionMerge %[[#bb140:]] None314; CHECK: OpBranchConditional %[[#]] %[[#bb141:]] %[[#bb142:]]315; CHECK: %[[#bb139:]] = OpLabel316; CHECK: %[[#bb141:]] = OpLabel317; CHECK: OpSelectionMerge %[[#bb143:]] None318; CHECK: OpSwitch %[[#]] %[[#bb143:]] 20 %[[#bb144:]] 21 %[[#bb145:]] 22 %[[#bb146:]] 23 %[[#bb147:]] 24 %[[#bb148:]] 25 %[[#bb149:]] 26 %[[#bb150:]] 27 %[[#bb151:]] 28 %[[#bb152:]] 29 %[[#bb153:]]319; CHECK: %[[#bb142:]] = OpLabel320; CHECK: %[[#bb144:]] = OpLabel321; CHECK: OpBranch %[[#bb143:]]322; CHECK: %[[#bb145:]] = OpLabel323; CHECK: OpBranch %[[#bb143:]]324; CHECK: %[[#bb146:]] = OpLabel325; CHECK: OpBranch %[[#bb143:]]326; CHECK: %[[#bb147:]] = OpLabel327; CHECK: OpBranch %[[#bb143:]]328; CHECK: %[[#bb148:]] = OpLabel329; CHECK: OpBranch %[[#bb143:]]330; CHECK: %[[#bb149:]] = OpLabel331; CHECK: OpBranch %[[#bb143:]]332; CHECK: %[[#bb150:]] = OpLabel333; CHECK: OpBranch %[[#bb143:]]334; CHECK: %[[#bb151:]] = OpLabel335; CHECK: OpBranch %[[#bb143:]]336; CHECK: %[[#bb152:]] = OpLabel337; CHECK: OpBranch %[[#bb143:]]338; CHECK: %[[#bb153:]] = OpLabel339; CHECK: OpBranch %[[#bb143:]]340; CHECK: %[[#bb143:]] = OpLabel341; CHECK: OpSelectionMerge %[[#bb154:]] None342; CHECK: OpSwitch %[[#]] %[[#bb154:]] 1 %[[#bb155:]] 2 %[[#bb156:]] 3 %[[#bb157:]]343; CHECK: %[[#bb155:]] = OpLabel344; CHECK: OpBranch %[[#bb154:]]345; CHECK: %[[#bb156:]] = OpLabel346; CHECK: OpBranch %[[#bb154:]]347; CHECK: %[[#bb157:]] = OpLabel348; CHECK: OpBranch %[[#bb154:]]349; CHECK: %[[#bb154:]] = OpLabel350; CHECK: OpBranch %[[#bb140:]]351; CHECK: %[[#bb140:]] = OpLabel352; CHECK: OpSelectionMerge %[[#bb158:]] None353; CHECK: OpSwitch %[[#]] %[[#bb158:]] 1 %[[#bb159:]] 2 %[[#bb160:]]354; CHECK: %[[#bb159:]] = OpLabel355; CHECK: OpBranch %[[#bb158:]]356; CHECK: %[[#bb160:]] = OpLabel357; CHECK: OpBranch %[[#bb158:]]358; CHECK: %[[#bb158:]] = OpLabel359; CHECK: OpBranch %[[#bb137:]]360; CHECK: %[[#bb137:]] = OpLabel361; CHECK: OpBranch %[[#bb134:]]362; CHECK: %[[#bb134:]] = OpLabel363; CHECK: OpSelectionMerge %[[#bb161:]] None364; CHECK: OpBranchConditional %[[#]] %[[#bb162:]] %[[#bb161:]]365; CHECK: %[[#bb162:]] = OpLabel366; CHECK: OpSelectionMerge %[[#bb163:]] None367; CHECK: OpBranchConditional %[[#]] %[[#bb164:]] %[[#bb165:]]368; CHECK: %[[#bb164:]] = OpLabel369; CHECK: OpSelectionMerge %[[#bb166:]] None370; CHECK: OpBranchConditional %[[#]] %[[#bb167:]] %[[#bb168:]]371; CHECK: %[[#bb165:]] = OpLabel372; CHECK: %[[#bb167:]] = OpLabel373; CHECK: OpSelectionMerge %[[#bb169:]] None374; CHECK: OpBranchConditional %[[#]] %[[#bb170:]] %[[#bb171:]]375; CHECK: %[[#bb168:]] = OpLabel376; CHECK: %[[#bb170:]] = OpLabel377; CHECK: OpSelectionMerge %[[#bb172:]] None378; CHECK: OpSwitch %[[#]] %[[#bb173:]] 50 %[[#bb172:]] 51 %[[#bb174:]] 52 %[[#bb175:]] 53 %[[#bb176:]] 54 %[[#bb177:]]379; CHECK: %[[#bb171:]] = OpLabel380; CHECK: %[[#bb173:]] = OpLabel381; CHECK: OpBranch %[[#bb172:]]382; CHECK: %[[#bb174:]] = OpLabel383; CHECK: OpBranch %[[#bb172:]]384; CHECK: %[[#bb175:]] = OpLabel385; CHECK: OpBranch %[[#bb172:]]386; CHECK: %[[#bb176:]] = OpLabel387; CHECK: OpBranch %[[#bb172:]]388; CHECK: %[[#bb177:]] = OpLabel389; CHECK: OpBranch %[[#bb172:]]390; CHECK: %[[#bb172:]] = OpLabel391; CHECK: OpSelectionMerge %[[#bb178:]] None392; CHECK: OpSwitch %[[#]] %[[#bb179:]] 1 %[[#bb178:]] 2 %[[#bb180:]] 3 %[[#bb181:]]393; CHECK: %[[#bb179:]] = OpLabel394; CHECK: OpBranch %[[#bb178:]]395; CHECK: %[[#bb180:]] = OpLabel396; CHECK: OpBranch %[[#bb178:]]397; CHECK: %[[#bb181:]] = OpLabel398; CHECK: OpBranch %[[#bb178:]]399; CHECK: %[[#bb178:]] = OpLabel400; CHECK: OpBranch %[[#bb169:]]401; CHECK: %[[#bb169:]] = OpLabel402; CHECK: OpSelectionMerge %[[#bb182:]] None403; CHECK: OpSwitch %[[#]] %[[#bb183:]] 1 %[[#bb182:]] 2 %[[#bb184:]]404; CHECK: %[[#bb183:]] = OpLabel405; CHECK: OpBranch %[[#bb182:]]406; CHECK: %[[#bb184:]] = OpLabel407; CHECK: OpBranch %[[#bb182:]]408; CHECK: %[[#bb182:]] = OpLabel409; CHECK: OpBranch %[[#bb166:]]410; CHECK: %[[#bb166:]] = OpLabel411; CHECK: OpBranchConditional %[[#]] %[[#bb185:]] %[[#bb163:]]412; CHECK: %[[#bb185:]] = OpLabel413; CHECK: OpBranch %[[#bb163:]]414; CHECK: %[[#bb163:]] = OpLabel415; CHECK: OpBranch %[[#bb161:]]416; CHECK: %[[#bb161:]] = OpLabel417; CHECK: OpSelectionMerge %[[#bb186:]] None418; CHECK: OpBranchConditional %[[#]] %[[#bb187:]] %[[#bb188:]]419; CHECK: %[[#bb187:]] = OpLabel420; CHECK: OpSelectionMerge %[[#bb189:]] None421; CHECK: OpSwitch %[[#]] %[[#bb189:]] 35 %[[#bb190:]] 115 %[[#bb191:]]422; CHECK: %[[#bb188:]] = OpLabel423; CHECK: %[[#bb190:]] = OpLabel424; CHECK: OpBranch %[[#bb189:]]425; CHECK: %[[#bb191:]] = OpLabel426; CHECK: OpBranch %[[#bb189:]]427; CHECK: %[[#bb189:]] = OpLabel428; CHECK: OpBranchConditional %[[#]] %[[#bb186:]] %[[#bb192:]]429; CHECK: %[[#bb192:]] = OpLabel430; CHECK: OpBranch %[[#bb186:]]431; CHECK: %[[#bb186:]] = OpLabel432; CHECK: OpSelectionMerge %[[#bb193:]] None433; CHECK: OpBranchConditional %[[#]] %[[#bb194:]] %[[#bb193:]]434; CHECK: %[[#bb194:]] = OpLabel435; CHECK: OpBranch %[[#bb193:]]436; CHECK: %[[#bb193:]] = OpLabel437; CHECK: OpReturn438; CHECK: OpFunctionEnd439; CHECK: %[[#func_80:]] = OpFunction %[[#void:]] None %[[#]]440; CHECK: %[[#bb195:]] = OpLabel441; CHECK: OpReturn442; CHECK: OpFunctionEnd443 444 445 446target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"447target triple = "spirv-unknown-vulkan1.3-compute"448 449; Function Attrs: convergent noinline norecurse nounwind optnone450define spir_func noundef i32 @_Z3foov() #0 {451entry:452 %0 = call token @llvm.experimental.convergence.entry()453 ret i32 200454}455 456; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)457declare token @llvm.experimental.convergence.entry() #1458 459; Function Attrs: convergent noinline norecurse nounwind optnone460define internal spir_func void @main() #0 {461entry:462 %0 = call token @llvm.experimental.convergence.entry()463 %result = alloca i32, align 4464 %a = alloca i32, align 4465 %c = alloca i32, align 4466 %r = alloca i32, align 4467 %s = alloca i32, align 4468 %t = alloca i32, align 4469 %sel = alloca float, align 4470 store i32 0, ptr %a, align 4471 %1 = load i32, ptr %a, align 4472 switch i32 %1, label %sw.default [473 i32 -3, label %sw.bb474 i32 0, label %sw.bb1475 i32 1, label %sw.bb2476 i32 2, label %sw.bb3477 ]478 479sw.bb: ; preds = %entry480 store i32 -300, ptr %result, align 4481 br label %sw.epilog482 483sw.bb1: ; preds = %entry484 store i32 0, ptr %result, align 4485 br label %sw.epilog486 487sw.bb2: ; preds = %entry488 store i32 100, ptr %result, align 4489 br label %sw.epilog490 491sw.bb3: ; preds = %entry492 %call4 = call spir_func noundef i32 @_Z3foov() #3 [ "convergencectrl"(token %0) ]493 store i32 %call4, ptr %result, align 4494 br label %sw.epilog495 496sw.default: ; preds = %entry497 store i32 777, ptr %result, align 4498 br label %sw.epilog499 500sw.epilog: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb501 %2 = load i32, ptr %a, align 4502 store i32 %2, ptr %c, align 4503 %3 = load i32, ptr %c, align 4504 switch i32 %3, label %sw.epilog7 [505 i32 -4, label %sw.bb5506 i32 4, label %sw.bb6507 ]508 509sw.bb5: ; preds = %sw.epilog510 store i32 -400, ptr %result, align 4511 br label %sw.epilog7512 513sw.bb6: ; preds = %sw.epilog514 store i32 400, ptr %result, align 4515 br label %sw.epilog7516 517sw.epilog7: ; preds = %sw.epilog, %sw.bb6, %sw.bb5518 %4 = load i32, ptr %a, align 4519 switch i32 %4, label %sw.epilog10 [520 i32 -5, label %sw.bb8521 i32 5, label %sw.bb9522 ]523 524sw.bb8: ; preds = %sw.epilog7525 store i32 -500, ptr %result, align 4526 br label %sw.bb9527 528sw.bb9: ; preds = %sw.epilog7, %sw.bb8529 store i32 500, ptr %result, align 4530 br label %sw.epilog10531 532sw.epilog10: ; preds = %sw.bb9, %sw.epilog7533 %5 = load i32, ptr %a, align 4534 switch i32 %5, label %sw.default14 [535 i32 6, label %sw.bb11536 i32 7, label %sw.bb12537 i32 8, label %sw.bb13538 ]539 540sw.bb11: ; preds = %sw.epilog10541 store i32 600, ptr %result, align 4542 br label %sw.bb12543 544sw.bb12: ; preds = %sw.epilog10, %sw.bb11545 store i32 700, ptr %result, align 4546 br label %sw.bb13547 548sw.bb13: ; preds = %sw.epilog10, %sw.bb12549 store i32 800, ptr %result, align 4550 br label %sw.epilog15551 552sw.default14: ; preds = %sw.epilog10553 store i32 777, ptr %result, align 4554 br label %sw.epilog15555 556sw.epilog15: ; preds = %sw.default14, %sw.bb13557 %6 = load i32, ptr %a, align 4558 switch i32 %6, label %sw.default17 [559 i32 10, label %sw.bb16560 i32 11, label %sw.bb16561 i32 12, label %sw.bb18562 ]563 564sw.bb16: ; preds = %sw.epilog15, %sw.epilog15565 br label %sw.default17566 567sw.default17: ; preds = %sw.epilog15, %sw.bb16568 br label %sw.bb18569 570sw.bb18: ; preds = %sw.epilog15, %sw.default17571 store i32 12, ptr %result, align 4572 br label %sw.epilog19573 574sw.epilog19: ; preds = %sw.bb18575 %7 = load i32, ptr %a, align 4576 switch i32 %7, label %sw.epilog21 [577 i32 15, label %sw.bb20578 i32 16, label %sw.bb20579 ]580 581sw.bb20: ; preds = %sw.epilog19, %sw.epilog19582 br label %sw.epilog21583 584sw.epilog21: ; preds = %sw.epilog19, %sw.bb20585 %8 = load i32, ptr %a, align 4586 switch i32 %8, label %sw.epilog29 [587 i32 20, label %sw.bb22588 i32 21, label %sw.bb23589 i32 22, label %sw.bb24590 i32 23, label %sw.bb24591 i32 24, label %sw.bb25592 i32 25, label %sw.bb25593 i32 26, label %sw.bb26594 i32 27, label %sw.bb26595 i32 28, label %sw.bb27596 i32 29, label %sw.bb28597 ]598 599sw.bb22: ; preds = %sw.epilog21600 store i32 20, ptr %result, align 4601 br label %sw.epilog29602 603sw.bb23: ; preds = %sw.epilog21604 store i32 21, ptr %result, align 4605 br label %sw.epilog29606 607sw.bb24: ; preds = %sw.epilog21, %sw.epilog21608 br label %sw.epilog29609 610sw.bb25: ; preds = %sw.epilog21, %sw.epilog21611 store i32 25, ptr %result, align 4612 br label %sw.epilog29613 614sw.bb26: ; preds = %sw.epilog21, %sw.epilog21615 br label %sw.epilog29616 617sw.bb27: ; preds = %sw.epilog21618 store i32 28, ptr %result, align 4619 br label %sw.epilog29620 621sw.bb28: ; preds = %sw.epilog21622 store i32 29, ptr %result, align 4623 br label %sw.epilog29624 625sw.epilog29: ; preds = %sw.epilog21, %sw.bb28, %sw.bb27, %sw.bb26, %sw.bb25, %sw.bb24, %sw.bb23, %sw.bb22626 %9 = load i32, ptr %a, align 4627 switch i32 %9, label %sw.epilog37 [628 i32 30, label %sw.bb30629 ]630 631sw.bb30: ; preds = %sw.epilog29632 store i32 30, ptr %result, align 4633 %10 = load i32, ptr %result, align 4634 switch i32 %10, label %sw.default31 [635 i32 50, label %sw.bb32636 i32 51, label %sw.bb33637 i32 52, label %sw.bb33638 i32 53, label %sw.bb34639 i32 54, label %sw.bb35640 ]641 642sw.default31: ; preds = %sw.bb30643 store i32 55, ptr %a, align 4644 br label %sw.bb32645 646sw.bb32: ; preds = %sw.bb30, %sw.default31647 store i32 50, ptr %a, align 4648 br label %sw.epilog36649 650sw.bb33: ; preds = %sw.bb30, %sw.bb30651 store i32 52, ptr %a, align 4652 br label %sw.bb34653 654sw.bb34: ; preds = %sw.bb30, %sw.bb33655 store i32 53, ptr %a, align 4656 br label %sw.epilog36657 658sw.bb35: ; preds = %sw.bb30659 store i32 54, ptr %a, align 4660 br label %sw.epilog36661 662sw.epilog36: ; preds = %sw.bb35, %sw.bb34, %sw.bb32663 br label %sw.epilog37664 665sw.epilog37: ; preds = %sw.epilog36, %sw.epilog29666 store i32 35, ptr %r, align 4667 store i32 45, ptr %s, align 4668 store i32 115, ptr %t, align 4669 %11 = load i32, ptr %a, align 4670 switch i32 %11, label %sw.epilog40 [671 i32 35, label %sw.bb38672 i32 115, label %sw.bb39673 ]674 675sw.bb38: ; preds = %sw.epilog37676 store i32 35, ptr %result, align 4677 br label %sw.bb39678 679sw.bb39: ; preds = %sw.epilog37, %sw.bb38680 store i32 115, ptr %result, align 4681 br label %sw.epilog40682 683sw.epilog40: ; preds = %sw.epilog37, %sw.bb39684 %12 = load float, ptr %sel, align 4685 %conv = fptosi float %12 to i32686 switch i32 %conv, label %sw.epilog42 [687 i32 0, label %sw.bb41688 ]689 690sw.bb41: ; preds = %sw.epilog40691 store i32 0, ptr %result, align 4692 br label %sw.epilog42693 694sw.epilog42: ; preds = %sw.epilog40, %sw.bb41695 ret void696}697 698; Function Attrs: convergent norecurse699define void @main.1() #2 {700entry:701 call void @main()702 ret void703}704 705attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }706attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }707attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }708attributes #3 = { convergent }709 710!llvm.module.flags = !{!0, !1, !2}711 712 713!0 = !{i32 1, !"wchar_size", i32 4}714!1 = !{i32 4, !"dx.disable_optimizations", i32 1}715!2 = !{i32 7, !"frame-pointer", i32 2}716 717 718