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1; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}3 4target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"5target triple = "spirv-unknown-vulkan-compute"6 7define internal spir_func void @main() #0 {8 9; CHECK-DAG: OpName %[[#idx:]] "idx"10; CHECK-DAG: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId11; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 012; CHECK-DAG: %[[#int_ipty:]] = OpTypePointer Input %[[#int_ty]]13; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool14; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 015; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 1016; CHECK-DAG: %[[#builtin]] = OpVariable %[[#int_ipty]] Input17 18; CHECK: %[[#entry:]] = OpLabel19; CHECK: %[[#idx]] = OpVariable %[[#]] Function20; ACHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 421; CHECK: OpBranch %[[#while_cond:]]22entry:23 %0 = call token @llvm.experimental.convergence.entry()24 %idx = alloca i32, align 425 store i32 0, ptr %idx, align 426 br label %while.cond27 28; CHECK: %[[#while_cond]] = OpLabel29; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 430; CHECK: %[[#cmp:]] = OpINotEqual %[[#bool_ty]] %[[#tmp]] %[[#int_10]]31; CHECK: OpLoopMerge %[[#new_end:]] %[[#if_end:]] None32; CHECK: OpBranchConditional %[[#cmp]] %[[#while_body:]] %[[#new_end]]33 34while.cond:35 %1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ]36 %2 = load i32, ptr %idx, align 437 %cmp = icmp ne i32 %2, 1038 br i1 %cmp, label %while.body, label %while.end39 40; CHECK: %[[#while_body]] = OpLabel41; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#builtin]] Aligned 142; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 443; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 444; CHECK: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]]45; CHECK: OpBranchConditional %[[#cmp1]] %[[#new_end]] %[[#if_end]]46while.body:47 %3 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ]48 store i32 %3, ptr %idx, align 449 %4 = load i32, ptr %idx, align 450 %cmp1 = icmp eq i32 %4, 051 br i1 %cmp1, label %if.then, label %if.end52 53; CHECK: %[[#if_end]] = OpLabel54; CHECK: OpBranch %[[#while_cond]]55 56; CHECK: %[[#new_end]] = OpLabel57; CHECK: OpBranch %[[#while_end:]]58if.then:59 br label %while.end60 61if.end:62 br label %while.cond63 64; CHECK: %[[#while_end]] = OpLabel65; CHECK: OpReturn66while.end:67 ret void68}69 70declare token @llvm.experimental.convergence.entry() #271declare token @llvm.experimental.convergence.loop() #272declare i32 @__hlsl_wave_get_lane_index() #373 74attributes #0 = { convergent noinline norecurse nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }75attributes #1 = { convergent norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }76attributes #2 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }77attributes #3 = { convergent }78 79!llvm.module.flags = !{!0, !1}80 81!0 = !{i32 1, !"wchar_size", i32 4}82!1 = !{i32 4, !"dx.disable_optimizations", i32 1}83