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1# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -run-pass=regallocbasic %s -o - | FileCheck %s2# This test used to assert in RABasic. The problem was when we split live-ranges,3# we were not updating the LiveRegMatrix properly and the interference calculation4# wouldn't match what the assignment thought it could do.5# In other words, this test case needs to trigger live-range splitting to exercise6# the problem.7#8# PR330579--- |10 target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"11 target triple = "s390x--linux-gnu"12 13 define void @autogen_SD21418() #0 {14 ret void15 }16 17 attributes #0 = { "target-cpu"="z13" }18 19...20 21# CHECK: name: autogen_SD2141822# Check that at least one live-range has been split23# CHECK: id: 114, class24---25name: autogen_SD2141826alignment: 427tracksRegLiveness: true28frameInfo:29 adjustsStack: true30registers: 31 - { id: 0, class: vr128bit }32 - { id: 1, class: vr128bit }33 - { id: 2, class: vr128bit }34 - { id: 3, class: vr64bit }35 - { id: 4, class: gr64bit }36 - { id: 5, class: vr128bit }37 - { id: 6, class: grx32bit }38 - { id: 7, class: vr128bit }39 - { id: 8, class: vr128bit }40 - { id: 9, class: gr32bit }41 - { id: 10, class: gr64bit }42 - { id: 11, class: vr128bit }43 - { id: 12, class: fp64bit }44 - { id: 13, class: vr64bit }45 - { id: 14, class: vr64bit }46 - { id: 15, class: gr64bit }47 - { id: 16, class: gr128bit }48 - { id: 17, class: gr64bit }49 - { id: 18, class: gr32bit }50 - { id: 19, class: gr32bit }51 - { id: 20, class: gr128bit }52 - { id: 21, class: gr32bit }53 - { id: 22, class: gr64bit }54 - { id: 23, class: gr32bit }55 - { id: 24, class: gr32bit }56 - { id: 25, class: gr128bit }57 - { id: 26, class: grx32bit }58 - { id: 27, class: gr64bit }59 - { id: 28, class: gr64bit }60 - { id: 29, class: vr128bit }61 - { id: 30, class: vr128bit }62 - { id: 31, class: gr64bit }63 - { id: 32, class: gr32bit }64 - { id: 33, class: gr32bit }65 - { id: 34, class: gr128bit }66 - { id: 35, class: gr32bit }67 - { id: 36, class: vr128bit }68 - { id: 37, class: gr64bit }69 - { id: 38, class: gr32bit }70 - { id: 39, class: gr32bit }71 - { id: 40, class: gr128bit }72 - { id: 41, class: gr32bit }73 - { id: 42, class: addr64bit }74 - { id: 43, class: grx32bit }75 - { id: 44, class: addr64bit }76 - { id: 45, class: vr64bit }77 - { id: 46, class: vr64bit }78 - { id: 47, class: gr32bit }79 - { id: 48, class: gr32bit }80 - { id: 49, class: grx32bit }81 - { id: 50, class: vr64bit }82 - { id: 51, class: gr64bit }83 - { id: 52, class: grx32bit }84 - { id: 53, class: gr32bit }85 - { id: 54, class: gr64bit }86 - { id: 55, class: grx32bit }87 - { id: 56, class: gr32bit }88 - { id: 57, class: gr128bit }89 - { id: 58, class: gr128bit }90 - { id: 59, class: gr32bit }91 - { id: 60, class: gr64bit }92 - { id: 61, class: grx32bit }93 - { id: 62, class: gr32bit }94 - { id: 63, class: gr64bit }95 - { id: 64, class: grx32bit }96 - { id: 65, class: gr32bit }97 - { id: 66, class: gr128bit }98 - { id: 67, class: gr128bit }99 - { id: 68, class: grx32bit }100 - { id: 69, class: gr64bit }101 - { id: 70, class: gr64bit }102 - { id: 71, class: vr128bit }103 - { id: 72, class: vr128bit }104 - { id: 73, class: gr64bit }105 - { id: 74, class: grx32bit }106 - { id: 75, class: gr32bit }107 - { id: 76, class: gr64bit }108 - { id: 77, class: grx32bit }109 - { id: 78, class: gr32bit }110 - { id: 79, class: gr128bit }111 - { id: 80, class: gr128bit }112 - { id: 81, class: gr32bit }113 - { id: 82, class: vr128bit }114 - { id: 83, class: gr64bit }115 - { id: 84, class: grx32bit }116 - { id: 85, class: gr32bit }117 - { id: 86, class: gr64bit }118 - { id: 87, class: grx32bit }119 - { id: 88, class: gr32bit }120 - { id: 89, class: gr128bit }121 - { id: 90, class: gr128bit }122 - { id: 91, class: gr32bit }123 - { id: 92, class: grx32bit }124 - { id: 93, class: gr64bit }125 - { id: 94, class: gr32bit }126 - { id: 95, class: gr32bit }127 - { id: 96, class: gr32bit }128 - { id: 97, class: gr64bit }129 - { id: 98, class: gr64bit }130 - { id: 99, class: grx32bit }131 - { id: 100, class: grx32bit }132 - { id: 101, class: gr128bit }133 - { id: 102, class: gr128bit }134 - { id: 103, class: gr128bit }135 - { id: 104, class: gr64bit }136 - { id: 105, class: gr128bit }137 - { id: 106, class: gr128bit }138 - { id: 107, class: gr64bit }139 - { id: 108, class: gr128bit }140 - { id: 109, class: gr128bit }141 - { id: 110, class: gr64bit }142 - { id: 111, class: gr128bit }143 - { id: 112, class: gr128bit }144 - { id: 113, class: gr64bit }145constants: 146 - id: 0147 value: double 0xD55960F86F577076148 alignment: 8149body: |150 bb.0:151 %11 = VGBM 0152 %43 = LHIMux 0153 %44 = LARL %const.0154 %45 = VL64 %44, 0, $noreg :: (load (s64) from constant-pool)155 156 bb.1:157 ADJCALLSTACKDOWN 0, 0158 %12 = LZDR159 $f0d = COPY %12160 CallBRASL &fmod, killed $f0d, undef $f2d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $f0d161 ADJCALLSTACKUP 0, 0162 KILL killed $f0d163 164 bb.2:165 %17 = VLGVH %11, $noreg, 0166 %19 = LHR %17.subreg_l32167 undef %20.subreg_l64 = LGHI 0168 %20 = DSGFR %20, %19169 %22 = VLGVH %11, $noreg, 3170 %24 = LHR %22.subreg_l32171 undef %25.subreg_l64 = LGHI 0172 %25 = DSGFR %25, %24173 %31 = VLGVH %11, $noreg, 1174 %33 = LHR %31.subreg_l32175 undef %34.subreg_l64 = LGHI 0176 %34 = DSGFR %34, %33177 %37 = VLGVH %11, $noreg, 2178 %39 = LHR %37.subreg_l32179 undef %40.subreg_l64 = LGHI 0180 %40 = DSGFR %40, %39181 CHIMux %43, 0, implicit-def $cc182 BRC 14, 6, %bb.2, implicit killed $cc183 J %bb.3184 185 bb.3:186 WFCDB undef %46, %45, implicit-def $cc, implicit $fpc187 %48 = IPM implicit killed $cc188 %48 = AFIMux %48, 268435456, implicit-def dead $cc189 %6 = RISBMux undef %6, %48, 31, 159, 35190 WFCDB undef %50, %45, implicit-def $cc, implicit $fpc191 BRC 15, 6, %bb.1, implicit killed $cc192 J %bb.4193 194 bb.4:195 %36 = VLVGP %25.subreg_l64, %25.subreg_l64196 %36 = VLVGH %36, %20.subreg_l32, $noreg, 0197 %36 = VLVGH %36, %34.subreg_l32, $noreg, 1198 dead %36 = VLVGH %36, %40.subreg_l32, $noreg, 2199 %4 = LG undef %42, 0, $noreg :: (load (s64) from `ptr undef`)200 undef %57.subreg_h64 = LLILL 0201 undef %66.subreg_h64 = LLILL 0202 undef %79.subreg_h64 = LLILL 0203 undef %89.subreg_h64 = LLILL 0204 %92 = LHIMux 0205 206 bb.5:207 208 bb.6:209 %51 = VLGVH undef %7, $noreg, 0210 %53 = LLHRMux %51.subreg_l32211 %54 = VLGVH undef %1, $noreg, 0212 %57.subreg_l32 = LLHRMux %54.subreg_l32213 %58 = COPY %57214 %58 = DLR %58, %53215 %60 = VLGVH undef %7, $noreg, 3216 %62 = LLHRMux %60.subreg_l32217 %63 = VLGVH undef %1, $noreg, 3218 %66.subreg_l32 = LLHRMux %63.subreg_l32219 %67 = COPY %66220 %67 = DLR %67, %62221 %73 = VLGVH undef %7, $noreg, 1222 %75 = LLHRMux %73.subreg_l32223 %76 = VLGVH undef %1, $noreg, 1224 %79.subreg_l32 = LLHRMux %76.subreg_l32225 %80 = COPY %79226 %80 = DLR %80, %75227 %83 = VLGVH undef %7, $noreg, 2228 %85 = LLHRMux %83.subreg_l32229 %86 = VLGVH undef %1, $noreg, 2230 %89.subreg_l32 = LLHRMux %86.subreg_l32231 %90 = COPY %89232 %90 = DLR %90, %85233 CHIMux %92, 0, implicit-def $cc234 BRC 14, 6, %bb.7, implicit killed $cc235 J %bb.6236 237 bb.7:238 CGHI undef %93, 0, implicit-def $cc239 %96 = IPM implicit killed $cc240 CGHI undef %97, 0, implicit-def $cc241 BRC 14, 6, %bb.6, implicit killed $cc242 243 bb.8:244 CHIMux %6, 0, implicit-def $cc245 %10 = LLILL 41639246 dead %10 = LOCGR %10, %4, 14, 6, implicit killed $cc247 CHIMux %92, 0, implicit-def $cc248 BRC 14, 6, %bb.5, implicit killed $cc249 J %bb.9250 251 bb.9:252 %82 = VLVGP %67.subreg_h64, %67.subreg_h64253 %82 = VLVGH %82, %58.subreg_l32, $noreg, 0254 %82 = VLVGH %82, %80.subreg_l32, $noreg, 1255 dead %82 = VLVGH %82, %90.subreg_l32, $noreg, 2256 %96 = AFIMux %96, 1879048192, implicit-def dead $cc257 %96 = SRL %96, $noreg, 31258 dead %11 = VLVGF %11, %96, $noreg, 1259 %100 = LHIMux 0260 261 bb.10:262 CHIMux %100, 0, implicit-def $cc263 BRC 14, 6, %bb.10, implicit killed $cc264 J %bb.11265 266 bb.11:267 Return268 269...270