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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; addr-01.ll in which the address is also used in a non-address context.3; The assumption here is that we should match complex addresses where4; possible, but this might well need to change in future.5;6; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s7 8; A simple index address.9define void @f1(i64 %addr, i64 %index, ptr %dst) {10; CHECK-LABEL: f1:11; CHECK:       # %bb.0:12; CHECK-NEXT:    lb %r0, 0(%r3,%r2)13; CHECK-NEXT:    la %r0, 0(%r3,%r2)14; CHECK-NEXT:    stg %r0, 0(%r4)15; CHECK-NEXT:    br %r1416  %add = add i64 %addr, %index17  %ptr = inttoptr i64 %add to ptr18  %a = load volatile i8, ptr %ptr19  store volatile ptr %ptr, ptr %dst20  ret void21}22 23; An address with an index and a displacement (order 1).24define void @f2(i64 %addr, i64 %index, ptr %dst) {25; CHECK-LABEL: f2:26; CHECK:       # %bb.0:27; CHECK-NEXT:    lb %r0, 100(%r3,%r2)28; CHECK-NEXT:    la %r0, 100(%r3,%r2)29; CHECK-NEXT:    stg %r0, 0(%r4)30; CHECK-NEXT:    br %r1431  %add1 = add i64 %addr, %index32  %add2 = add i64 %add1, 10033  %ptr = inttoptr i64 %add2 to ptr34  %a = load volatile i8, ptr %ptr35  store volatile ptr %ptr, ptr %dst36  ret void37}38 39; An address with an index and a displacement (order 2).40define void @f3(i64 %addr, i64 %index, ptr %dst) {41; CHECK-LABEL: f3:42; CHECK:       # %bb.0:43; CHECK-NEXT:    lb %r0, 100(%r3,%r2)44; CHECK-NEXT:    la %r0, 100(%r3,%r2)45; CHECK-NEXT:    stg %r0, 0(%r4)46; CHECK-NEXT:    br %r1447  %add1 = add i64 %addr, 10048  %add2 = add i64 %add1, %index49  %ptr = inttoptr i64 %add2 to ptr50  %a = load volatile i8, ptr %ptr51  store volatile ptr %ptr, ptr %dst52  ret void53}54 55; An address with an index and a subtracted displacement (order 1).56define void @f4(i64 %addr, i64 %index, ptr %dst) {57; CHECK-LABEL: f4:58; CHECK:       # %bb.0:59; CHECK-NEXT:    lb %r0, -100(%r3,%r2)60; CHECK-NEXT:    lay %r0, -100(%r3,%r2)61; CHECK-NEXT:    stg %r0, 0(%r4)62; CHECK-NEXT:    br %r1463  %add1 = add i64 %addr, %index64  %add2 = sub i64 %add1, 10065  %ptr = inttoptr i64 %add2 to ptr66  %a = load volatile i8, ptr %ptr67  store volatile ptr %ptr, ptr %dst68  ret void69}70 71; An address with an index and a subtracted displacement (order 2).72define void @f5(i64 %addr, i64 %index, ptr %dst) {73; CHECK-LABEL: f5:74; CHECK:       # %bb.0:75; CHECK-NEXT:    lb %r0, -100(%r3,%r2)76; CHECK-NEXT:    lay %r0, -100(%r3,%r2)77; CHECK-NEXT:    stg %r0, 0(%r4)78; CHECK-NEXT:    br %r1479  %add1 = sub i64 %addr, 10080  %add2 = add i64 %add1, %index81  %ptr = inttoptr i64 %add2 to ptr82  %a = load volatile i8, ptr %ptr83  store volatile ptr %ptr, ptr %dst84  ret void85}86 87; An address with an index and a displacement added using OR.88define void @f6(i64 %addr, i64 %index, ptr %dst) {89; CHECK-LABEL: f6:90; CHECK:       # %bb.0:91; CHECK-NEXT:    nill %r2, 6552892; CHECK-NEXT:    lb %r0, 6(%r2,%r3)93; CHECK-NEXT:    la %r0, 6(%r2,%r3)94; CHECK-NEXT:    stg %r0, 0(%r4)95; CHECK-NEXT:    br %r1496  %aligned = and i64 %addr, -897  %or = or i64 %aligned, 698  %add = add i64 %or, %index99  %ptr = inttoptr i64 %add to ptr100  %a = load volatile i8, ptr %ptr101  store volatile ptr %ptr, ptr %dst102  ret void103}104 105; Like f6, but without the masking.  This OR doesn't count as a displacement.106define void @f7(i64 %addr, i64 %index, ptr %dst) {107; CHECK-LABEL: f7:108; CHECK:       # %bb.0:109; CHECK-NEXT:    oill %r2, 6110; CHECK-NEXT:    lb %r0, 0(%r3,%r2)111; CHECK-NEXT:    la %r0, 0(%r3,%r2)112; CHECK-NEXT:    stg %r0, 0(%r4)113; CHECK-NEXT:    br %r14114  %or = or i64 %addr, 6115  %add = add i64 %or, %index116  %ptr = inttoptr i64 %add to ptr117  %a = load volatile i8, ptr %ptr118  store volatile ptr %ptr, ptr %dst119  ret void120}121 122; Like f6, but with the OR applied after the index.  We don't know anything123; about the alignment of %add here.124define void @f8(i64 %addr, i64 %index, ptr %dst) {125; CHECK-LABEL: f8:126; CHECK:       # %bb.0:127; CHECK-NEXT:    nill %r2, 65528128; CHECK-NEXT:    agr %r2, %r3129; CHECK-NEXT:    oill %r2, 6130; CHECK-NEXT:    lb %r0, 0(%r2)131; CHECK-NEXT:    stg %r2, 0(%r4)132; CHECK-NEXT:    br %r14133  %aligned = and i64 %addr, -8134  %add = add i64 %aligned, %index135  %or = or i64 %add, 6136  %ptr = inttoptr i64 %or to ptr137  %a = load volatile i8, ptr %ptr138  store volatile ptr %ptr, ptr %dst139  ret void140}141