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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; Test complex addresses with base or index truncated from 128 bit.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6; Shift amount with base truncated from 128 bit to 32 bit.7define void @f1(i128 %x, i32 %y, ptr %px, ptr %py) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: larl %r1, .LCPI0_011; CHECK-NEXT: vl %v0, 0(%r2), 312; CHECK-NEXT: vl %v1, 0(%r1), 313; CHECK-NEXT: vaq %v0, %v0, %v114; CHECK-NEXT: vlgvf %r1, %v0, 315; CHECK-NEXT: srl %r3, 0(%r1)16; CHECK-NEXT: vst %v0, 0(%r4), 317; CHECK-NEXT: st %r3, 0(%r5)18; CHECK-NEXT: br %r1419 %x1 = add i128 %x, 120 store i128 %x1, ptr %px, align 821 %amt = trunc i128 %x1 to i3222 %y1 = lshr i32 %y, %amt23 store i32 %y1, ptr %py, align 424 ret void25}26 27; Memory address with index truncated from 128 bit to 64 bit.28define i8 @f2(ptr %base, ptr %p) {29; CHECK-LABEL: f2:30; CHECK: # %bb.0:31; CHECK-NEXT: larl %r1, .LCPI1_032; CHECK-NEXT: vl %v0, 0(%r3), 333; CHECK-NEXT: vl %v1, 0(%r1), 334; CHECK-NEXT: vaq %v0, %v0, %v135; CHECK-NEXT: vlgvg %r1, %v0, 136; CHECK-NEXT: vst %v0, 0(%r3), 337; CHECK-NEXT: lb %r2, 0(%r1,%r2)38; CHECK-NEXT: br %r1439 %idx = load i128, ptr %p, align 840 %inc = add nsw i128 %idx, 141 store i128 %inc, ptr %p, align 842 %idxprom = trunc i128 %inc to i6443 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %idxprom44 %res = load i8, ptr %arrayidx, align 145 ret i8 %res46}47