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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test 128-bit AND / AND-NOT in vector registers on z133;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6; And.7define i128 @f1(i128 %a, i128 %b) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl %v0, 0(%r4), 311; CHECK-NEXT: vl %v1, 0(%r3), 312; CHECK-NEXT: vn %v0, %v1, %v013; CHECK-NEXT: vst %v0, 0(%r2), 314; CHECK-NEXT: br %r1415 %res = and i128 %a, %b16 ret i128 %res17}18 19; And with complement.20define i128 @f2(i128 %a, i128 %b) {21; CHECK-LABEL: f2:22; CHECK: # %bb.0:23; CHECK-NEXT: vl %v0, 0(%r4), 324; CHECK-NEXT: vl %v1, 0(%r3), 325; CHECK-NEXT: vnc %v0, %v1, %v026; CHECK-NEXT: vst %v0, 0(%r2), 327; CHECK-NEXT: br %r1428 %notb = xor i128 %b, -129 %res = and i128 %a, %notb30 ret i128 %res31}32