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1; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s2 3; Stackmap Header: no constants - 6 callsites4; CHECK: .section .llvm_stackmaps5; CHECK-NEXT: __LLVM_StackMaps:6; Header7; CHECK-NEXT: .byte 38; CHECK-NEXT: .byte 09; CHECK-NEXT: .short 010; Num Functions11; CHECK-NEXT: .long 812; Num Constants13; CHECK-NEXT: .long 014; Num Callsites15; CHECK-NEXT: .long 816 17; Functions and stack size18; CHECK-NEXT: .quad test19; CHECK-NEXT: .quad 16020; CHECK-NEXT: .quad 121; CHECK-NEXT: .quad property_access122; CHECK-NEXT: .quad 16023; CHECK-NEXT: .quad 124; CHECK-NEXT: .quad property_access225; CHECK-NEXT: .quad 16826; CHECK-NEXT: .quad 127; CHECK-NEXT: .quad property_access328; CHECK-NEXT: .quad 16829; CHECK-NEXT: .quad 130; CHECK-NEXT: .quad anyreg_test131; CHECK-NEXT: .quad 16032; CHECK-NEXT: .quad 133; CHECK-NEXT: .quad anyreg_test234; CHECK-NEXT: .quad 16035; CHECK-NEXT: .quad 136; CHECK-NEXT: .quad patchpoint_spilldef37; CHECK-NEXT: .quad 16838; CHECK-NEXT: .quad 139; CHECK-NEXT: .quad patchpoint_spillargs40; CHECK-NEXT: .quad 19241; CHECK-NEXT: .quad 142 43; No constants44 45; Callsites46; test47; CHECK: .long .L{{.*}}-test48; CHECK-NEXT: .short 049; 3 locations50; CHECK-NEXT: .short 351; Loc 0: Register52; CHECK-NEXT: .byte 153; CHECK-NEXT: .byte 054; CHECK-NEXT: .short 455; CHECK-NEXT: .short {{[0-9]+}}56; CHECK-NEXT: .short 057; CHECK-NEXT: .long 058; Loc 1: Register59; CHECK-NEXT: .byte 160; CHECK-NEXT: .byte 061; CHECK-NEXT: .short 462; CHECK-NEXT: .short {{[0-9]+}}63; CHECK-NEXT: .short 064; CHECK-NEXT: .long 065; Loc 2: Constant 366; CHECK-NEXT: .byte 467; CHECK-NEXT: .byte 068; CHECK-NEXT: .short 869; CHECK-NEXT: .short 070; CHECK-NEXT: .short 071; CHECK-NEXT: .long 372define i64 @test() nounwind ssp uwtable {73entry:74 call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 14, ptr null, i32 2, i32 1, i32 2, i64 3)75 ret i64 076}77 78; property access 1 - %obj is an anyreg call argument and should therefore be in a register79; CHECK: .long .L{{.*}}-property_access180; CHECK-NEXT: .short 081; 2 locations82; CHECK-NEXT: .short 283; Loc 0: Register <-- this is the return register84; CHECK-NEXT: .byte 185; CHECK-NEXT: .byte 086; CHECK-NEXT: .short 887; CHECK-NEXT: .short {{[0-9]+}}88; CHECK-NEXT: .short 089; CHECK-NEXT: .long 090; Loc 1: Register91; CHECK-NEXT: .byte 192; CHECK-NEXT: .byte 093; CHECK-NEXT: .short 894; CHECK-NEXT: .short {{[0-9]+}}95; CHECK-NEXT: .short 096; CHECK-NEXT: .long 097define i64 @property_access1(ptr %obj) nounwind ssp uwtable {98entry:99 %f = inttoptr i64 12297829382473034410 to ptr100 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 14, ptr %f, i32 1, ptr %obj)101 ret i64 %ret102}103 104; property access 2 - %obj is an anyreg call argument and should therefore be in a register105; CHECK: .long .L{{.*}}-property_access2106; CHECK-NEXT: .short 0107; 2 locations108; CHECK-NEXT: .short 2109; Loc 0: Register <-- this is the return register110; CHECK-NEXT: .byte 1111; CHECK-NEXT: .byte 0112; CHECK-NEXT: .short 8113; CHECK-NEXT: .short {{[0-9]+}}114; CHECK-NEXT: .short 0115; CHECK-NEXT: .long 0116; Loc 1: Register117; CHECK-NEXT: .byte 1118; CHECK-NEXT: .byte 0119; CHECK-NEXT: .short 8120; CHECK-NEXT: .short {{[0-9]+}}121; CHECK-NEXT: .short 0122; CHECK-NEXT: .long 0123define i64 @property_access2() nounwind ssp uwtable {124entry:125 %obj = alloca i64, align 8126 %f = inttoptr i64 12297829382473034410 to ptr127 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 14, ptr %f, i32 1, ptr %obj)128 ret i64 %ret129}130 131; property access 3 - %obj is a frame index132; CHECK: .long .L{{.*}}-property_access3133; CHECK-NEXT: .short 0134; 2 locations135; CHECK-NEXT: .short 2136; Loc 0: Register <-- this is the return register137; CHECK-NEXT: .byte 1138; CHECK-NEXT: .byte 0139; CHECK-NEXT: .short 8140; CHECK-NEXT: .short {{[0-9]+}}141; CHECK-NEXT: .short 0142; CHECK-NEXT: .long 0143; Loc 1: Direct %r15 + 160144; CHECK-NEXT: .byte 2145; CHECK-NEXT: .byte 0146; CHECK-NEXT: .short 8147; CHECK-NEXT: .short 15148; CHECK-NEXT: .short 0149; CHECK-NEXT: .long 160150define i64 @property_access3() nounwind ssp uwtable {151entry:152 %obj = alloca i64, align 8153 %f = inttoptr i64 12297829382473034410 to ptr154 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 14, ptr %f, i32 0, ptr %obj)155 ret i64 %ret156}157 158; anyreg_test1159; CHECK: .long .L{{.*}}-anyreg_test1160; CHECK-NEXT: .short 0161; 13 locations162; CHECK-NEXT: .short 13163; Loc 0: Register <-- this is the return register164; CHECK-NEXT: .byte 1165; CHECK-NEXT: .byte 0166; CHECK-NEXT: .short 8167; CHECK-NEXT: .short {{[0-9]+}}168; CHECK-NEXT: .short 0169; CHECK-NEXT: .long 0170; Loc 1: Register171; CHECK-NEXT: .byte 1172; CHECK-NEXT: .byte 0173; CHECK-NEXT: .short 8174; CHECK-NEXT: .short {{[0-9]+}}175; CHECK-NEXT: .short 0176; CHECK-NEXT: .long 0177; Loc 2: Register178; CHECK-NEXT: .byte 1179; CHECK-NEXT: .byte 0180; CHECK-NEXT: .short 8181; CHECK-NEXT: .short {{[0-9]+}}182; CHECK-NEXT: .short 0183; CHECK-NEXT: .long 0184; Loc 3: Register185; CHECK-NEXT: .byte 1186; CHECK-NEXT: .byte 0187; CHECK-NEXT: .short 8188; CHECK-NEXT: .short {{[0-9]+}}189; CHECK-NEXT: .short 0190; CHECK-NEXT: .long 0191; Loc 4: Register192; CHECK-NEXT: .byte 1193; CHECK-NEXT: .byte 0194; CHECK-NEXT: .short 8195; CHECK-NEXT: .short {{[0-9]+}}196; CHECK-NEXT: .short 0197; CHECK-NEXT: .long 0198; Loc 5: Register199; CHECK-NEXT: .byte 1200; CHECK-NEXT: .byte 0201; CHECK-NEXT: .short 8202; CHECK-NEXT: .short {{[0-9]+}}203; CHECK-NEXT: .short 0204; CHECK-NEXT: .long 0205; Loc 6: Register206; CHECK-NEXT: .byte 1207; CHECK-NEXT: .byte 0208; CHECK-NEXT: .short 8209; CHECK-NEXT: .short {{[0-9]+}}210; CHECK-NEXT: .short 0211; CHECK-NEXT: .long 0212; Loc 7: Register213; CHECK-NEXT: .byte 1214; CHECK-NEXT: .byte 0215; CHECK-NEXT: .short 8216; CHECK-NEXT: .short {{[0-9]+}}217; CHECK-NEXT: .short 0218; CHECK-NEXT: .long 0219; Loc 8: Register220; CHECK-NEXT: .byte 1221; CHECK-NEXT: .byte 0222; CHECK-NEXT: .short 8223; CHECK-NEXT: .short {{[0-9]+}}224; CHECK-NEXT: .short 0225; CHECK-NEXT: .long 0226; Loc 9: Register227; CHECK-NEXT: .byte 1228; CHECK-NEXT: .byte 0229; CHECK-NEXT: .short 8230; CHECK-NEXT: .short {{[0-9]+}}231; CHECK-NEXT: .short 0232; CHECK-NEXT: .long 0233; Loc 10: Register234; CHECK-NEXT: .byte 1235; CHECK-NEXT: .byte 0236; CHECK-NEXT: .short 8237; CHECK-NEXT: .short {{[0-9]+}}238; CHECK-NEXT: .short 0239; CHECK-NEXT: .long 0240; Loc 11: Register241; CHECK-NEXT: .byte 1242; CHECK-NEXT: .byte 0243; CHECK-NEXT: .short 8244; CHECK-NEXT: .short {{[0-9]+}}245; CHECK-NEXT: .short 0246; CHECK-NEXT: .long 0247; Loc 12: Register248; CHECK-NEXT: .byte 1249; CHECK-NEXT: .byte 0250; CHECK-NEXT: .short 8251; CHECK-NEXT: .short {{[0-9]+}}252; CHECK-NEXT: .short 0253; CHECK-NEXT: .long 0254define i64 @anyreg_test1(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12) nounwind ssp uwtable {255entry:256 %f = inttoptr i64 12297829382473034410 to ptr257 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 14, ptr %f, i32 12, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12)258 ret i64 %ret259}260 261; anyreg_test2262; CHECK: .long .L{{.*}}-anyreg_test2263; CHECK-NEXT: .short 0264; 13 locations265; CHECK-NEXT: .short 13266; Loc 0: Register <-- this is the return register267; CHECK-NEXT: .byte 1268; CHECK-NEXT: .byte 0269; CHECK-NEXT: .short 8270; CHECK-NEXT: .short {{[0-9]+}}271; CHECK-NEXT: .short 0272; CHECK-NEXT: .long 0273; Loc 1: Register274; CHECK-NEXT: .byte 1275; CHECK-NEXT: .byte 0276; CHECK-NEXT: .short 8277; CHECK-NEXT: .short {{[0-9]+}}278; CHECK-NEXT: .short 0279; CHECK-NEXT: .long 0280; Loc 2: Register281; CHECK-NEXT: .byte 1282; CHECK-NEXT: .byte 0283; CHECK-NEXT: .short 8284; CHECK-NEXT: .short {{[0-9]+}}285; CHECK-NEXT: .short 0286; CHECK-NEXT: .long 0287; Loc 3: Register288; CHECK-NEXT: .byte 1289; CHECK-NEXT: .byte 0290; CHECK-NEXT: .short 8291; CHECK-NEXT: .short {{[0-9]+}}292; CHECK-NEXT: .short 0293; CHECK-NEXT: .long 0294; Loc 4: Register295; CHECK-NEXT: .byte 1296; CHECK-NEXT: .byte 0297; CHECK-NEXT: .short 8298; CHECK-NEXT: .short {{[0-9]+}}299; CHECK-NEXT: .short 0300; CHECK-NEXT: .long 0301; Loc 5: Register302; CHECK-NEXT: .byte 1303; CHECK-NEXT: .byte 0304; CHECK-NEXT: .short 8305; CHECK-NEXT: .short {{[0-9]+}}306; CHECK-NEXT: .short 0307; CHECK-NEXT: .long 0308; Loc 6: Register309; CHECK-NEXT: .byte 1310; CHECK-NEXT: .byte 0311; CHECK-NEXT: .short 8312; CHECK-NEXT: .short {{[0-9]+}}313; CHECK-NEXT: .short 0314; CHECK-NEXT: .long 0315; Loc 7: Register316; CHECK-NEXT: .byte 1317; CHECK-NEXT: .byte 0318; CHECK-NEXT: .short 8319; CHECK-NEXT: .short {{[0-9]+}}320; CHECK-NEXT: .short 0321; CHECK-NEXT: .long 0322; Loc 8: Register323; CHECK-NEXT: .byte 1324; CHECK-NEXT: .byte 0325; CHECK-NEXT: .short 8326; CHECK-NEXT: .short 13327; CHECK-NEXT: .short 0328; CHECK-NEXT: .long 0329; Loc 9: IndirectMem330; CHECK-NEXT: .byte 3331; CHECK-NEXT: .byte 0332; CHECK-NEXT: .short 8333; CHECK-NEXT: .short {{[0-9]+}}334; CHECK-NEXT: .short 0335; CHECK-NEXT: .long 344336; Loc 10: IndirectMem337; CHECK-NEXT: .byte 3338; CHECK-NEXT: .byte 0339; CHECK-NEXT: .short 8340; CHECK-NEXT: .short {{[0-9]+}}341; CHECK-NEXT: .short 0342; CHECK-NEXT: .long 352343; Loc 11: IndirectMem344; CHECK-NEXT: .byte 3345; CHECK-NEXT: .byte 0346; CHECK-NEXT: .short 8347; CHECK-NEXT: .short {{[0-9]+}}348; CHECK-NEXT: .short 0349; CHECK-NEXT: .long 360350; Loc 12: IndirectMem351; CHECK-NEXT: .byte 3352; CHECK-NEXT: .byte 0353; CHECK-NEXT: .short 8354; CHECK-NEXT: .short {{[0-9]+}}355; CHECK-NEXT: .short 0356; CHECK-NEXT: .long 368357define i64 @anyreg_test2(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12) nounwind ssp uwtable {358entry:359 %f = inttoptr i64 12297829382473034410 to ptr360 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 14, ptr %f, i32 8, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12)361 ret i64 %ret362}363 364; Test spilling the return value of an anyregcc call.365;366; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"367;368; CHECK: .long .L{{.*}}-patchpoint_spilldef369; CHECK-NEXT: .short 0370; CHECK-NEXT: .short 3371; Loc 0: Register (some register that will be spilled to the stack)372; CHECK-NEXT: .byte 1373; CHECK-NEXT: .byte 0374; CHECK-NEXT: .short 8375; CHECK-NEXT: .short {{[0-9]+}}376; CHECK-NEXT: .short 0377; CHECK-NEXT: .long 0378; Loc 1: Register %r2379; CHECK-NEXT: .byte 1380; CHECK-NEXT: .byte 0381; CHECK-NEXT: .short 8382; CHECK-NEXT: .short 2383; CHECK-NEXT: .short 0384; CHECK-NEXT: .long 0385; Loc 1: Register %r3386; CHECK-NEXT: .byte 1387; CHECK-NEXT: .byte 0388; CHECK-NEXT: .short 8389; CHECK-NEXT: .short 3390; CHECK-NEXT: .short 0391; CHECK-NEXT: .long 0392define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {393entry:394 %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 14, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2)395 tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind396 ret i64 %result397}398 399; Test spilling the arguments of an anyregcc call.400;401; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled402;403; CHECK: .long .L{{.*}}-patchpoint_spillargs404; CHECK-NEXT: .short 0405; CHECK-NEXT: .short 5406; Loc 0: Return a register407; CHECK-NEXT: .byte 1408; CHECK-NEXT: .byte 0409; CHECK-NEXT: .short 8410; CHECK-NEXT: .short {{[0-9]+}}411; CHECK-NEXT: .short 0412; CHECK-NEXT: .long 0413; Loc 1: Arg0 in a Register414; CHECK-NEXT: .byte 1415; CHECK-NEXT: .byte 0416; CHECK-NEXT: .short 8417; CHECK-NEXT: .short {{[0-9]+}}418; CHECK-NEXT: .short 0419; CHECK-NEXT: .long 0420; Loc 2: Arg1 in a Register421; CHECK-NEXT: .byte 1422; CHECK-NEXT: .byte 0423; CHECK-NEXT: .short 8424; CHECK-NEXT: .short {{[0-9]+}}425; CHECK-NEXT: .short 0426; CHECK-NEXT: .long 0427; Loc 3: Arg2 spilled to %r15 +428; CHECK-NEXT: .byte 3429; CHECK-NEXT: .byte 0430; CHECK-NEXT: .short 8431; CHECK-NEXT: .short 15432; CHECK-NEXT: .short 0433; CHECK-NEXT: .long434; Loc 4: Arg3 spilled to %r15 +435; CHECK-NEXT: .byte 3436; CHECK-NEXT: .byte 0437; CHECK-NEXT: .short 8438; CHECK-NEXT: .short 15439; CHECK-NEXT: .short 0440; CHECK-NEXT: .long441define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {442entry:443 tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind444 %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 14, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)445 ret i64 %result446}447 448declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)449declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)450