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1; Test the vector constraint "v" and explicit vector register names.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-integrated-as | FileCheck %s4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-integrated-as | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-Z145 6define half @f0() {7; CHECK-LABEL: f0:8; CHECK: lzer %f19; CHECK: blah %f0 %f110; CHECK: br %r1411 %val = call half asm "blah $0 $1", "=&v,v" (half 0.0)12 ret half %val13}14 15define float @f1() {16; CHECK-LABEL: f1:17; CHECK: lzer %f118; CHECK: blah %f0 %f119; CHECK: br %r1420 %val = call float asm "blah $0 $1", "=&v,v" (float 0.0)21 ret float %val22}23 24define double @f2() {25; CHECK-LABEL: f2:26; CHECK: lzdr %f127; CHECK: blah %f0 %f128; CHECK: br %r1429 %val = call double asm "blah $0 $1", "=&v,v" (double 0.0)30 ret double %val31}32 33define fp128 @f3() {34; CHECK-LABEL: f3:35; CHECK-Z14: vzero %v036; CHECK: blah %v1 %v037; CHECK: vst %v1, 0(%r2)38; CHECK: br %r1439 %val = call fp128 asm "blah $0 $1", "=&v,v" (fp128 0xL00000000000000000000000000000000)40 ret fp128 %val41}42 43define <2 x i64> @f4() {44; CHECK-LABEL: f4:45; CHECK: vrepig %v0, 146; CHECK: blah %v24 %v047; CHECK: br %r1448 %val = call <2 x i64> asm "blah $0 $1", "=&v,v" (<2 x i64> <i64 1, i64 1>)49 ret <2 x i64> %val50}51 52define <4 x i32> @f5() {53; CHECK-LABEL: f5:54; CHECK: vrepif %v0, 155; CHECK: blah %v24 %v056; CHECK: br %r1457 %val = call <4 x i32> asm "blah $0 $1", "=&v,v" (<4 x i32> <i32 1, i32 1, i32 1, i32 1>)58 ret <4 x i32> %val59}60 61define <8 x i16> @f6() {62; CHECK-LABEL: f6:63; CHECK: vrepih %v0, 164; CHECK: blah %v24 %v065; CHECK: br %r1466 %val = call <8 x i16> asm "blah $0 $1", "=&v,v" (<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)67 ret <8 x i16> %val68}69 70define <16 x i8> @f7() {71; CHECK-LABEL: f7:72; CHECK: vrepib %v0, 173; CHECK: blah %v24 %v074; CHECK: br %r1475 %val = call <16 x i8> asm "blah $0 $1", "=&v,v" (<16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,76 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)77 ret <16 x i8> %val78}79 80define <2 x double> @f8() {81; CHECK-LABEL: f8:82; CHECK: vgbm %v0, 083; CHECK: blah %v24 %v084; CHECK: br %r1485 %val = call <2 x double> asm "blah $0 $1", "=&v,v" (<2 x double> <double 0.0, double 0.0>)86 ret <2 x double> %val87}88 89define <4 x float> @f9() {90; CHECK-LABEL: f9:91; CHECK: vgbm %v0, 092; CHECK: blah %v24 %v093; CHECK: br %r1494 %val = call <4 x float> asm "blah $0 $1", "=&v,v" (<4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>)95 ret <4 x float> %val96}97 98define half @f10_half() {99; CHECK-LABEL: f10_half:100; CHECK: lzer %f4101; CHECK: blah %f4102; CHECK: ldr %f0, %f4103; CHECK: br %r14104 %ret = call half asm "blah $0", "={v4},0" (half 0.0)105 ret half %ret106}107 108define float @f10() {109; CHECK-LABEL: f10:110; CHECK: lzer %f4111; CHECK: blah %f4112; CHECK: ldr %f0, %f4113; CHECK: br %r14114 %ret = call float asm "blah $0", "={v4},0" (float 0.0)115 ret float %ret116}117 118define double @f11() {119; CHECK-LABEL: f11:120; CHECK: lzdr %f4121; CHECK: blah %f4122; CHECK: ldr %f0, %f4123; CHECK: br %r14124 %ret = call double asm "blah $0", "={v4},0" (double 0.0)125 ret double %ret126}127 128define fp128 @f12() {129; CHECK-LABEL: f12:130; CHECK-Z14: vzero %v4131; CHECK: blah %v4132; CHECK: vst %v4, 0(%r2)133; CHECK: br %r14134 %ret = call fp128 asm "blah $0", "={v4},0" (fp128 0xL00000000000000000000000000000000)135 ret fp128 %ret136}137 138define <2 x i64> @f13() {139; CHECK-LABEL: f13:140; CHECK: vrepig %v4, 1141; CHECK: blah %v4142; CHECK: vlr %v24, %v4143; CHECK: br %r14144 %ret = call <2 x i64> asm "blah $0", "={v4},0" (<2 x i64> <i64 1, i64 1>)145 ret <2 x i64> %ret146}147 148define <2 x i64> @f14(<2 x i64> %in) {149; CHECK-LABEL: f14:150; CHECK: vlr [[REG:%v[0-9]+]], %v24151; CHECK: blah152; CHECK: vlr %v24, [[REG]]153; CHECK: br %r14154 call void asm sideeffect "blah", "~{v24},~{cc}"()155 ret <2 x i64> %in156}157 158