158 lines · plain
1; Test all condition-code masks that are relevant for CGRJ.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5declare i64 @foo()6 7; Test EQ.8define void @f1(i64 %target) {9; CHECK-LABEL: f1:10; CHECK: .cfi_def_cfa_offset11; CHECK: .L[[LABEL:.*]]:12; CHECK: cgrje %r2, {{%r[0-9]+}}, .L[[LABEL]]13 br label %loop14loop:15 %val = call i64 @foo()16 %cond = icmp eq i64 %val, %target17 br i1 %cond, label %loop, label %exit18exit:19 ret void20}21 22; Test NE.23define void @f2(i64 %target) {24; CHECK-LABEL: f2:25; CHECK: .cfi_def_cfa_offset26; CHECK: .L[[LABEL:.*]]:27; CHECK: cgrjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]28 br label %loop29loop:30 %val = call i64 @foo()31 %cond = icmp ne i64 %val, %target32 br i1 %cond, label %loop, label %exit33exit:34 ret void35}36 37; Test SLE.38define void @f3(i64 %target) {39; CHECK-LABEL: f3:40; CHECK: .cfi_def_cfa_offset41; CHECK: .L[[LABEL:.*]]:42; CHECK: cgrjle %r2, {{%r[0-9]+}}, .L[[LABEL]]43 br label %loop44loop:45 %val = call i64 @foo()46 %cond = icmp sle i64 %val, %target47 br i1 %cond, label %loop, label %exit48exit:49 ret void50}51 52; Test SLT.53define void @f4(i64 %target) {54; CHECK-LABEL: f4:55; CHECK: .cfi_def_cfa_offset56; CHECK: .L[[LABEL:.*]]:57; CHECK: cgrjl %r2, {{%r[0-9]+}}, .L[[LABEL]]58 br label %loop59loop:60 %val = call i64 @foo()61 %cond = icmp slt i64 %val, %target62 br i1 %cond, label %loop, label %exit63exit:64 ret void65}66 67; Test SGT.68define void @f5(i64 %target) {69; CHECK-LABEL: f5:70; CHECK: .cfi_def_cfa_offset71; CHECK: .L[[LABEL:.*]]:72; CHECK: cgrjh %r2, {{%r[0-9]+}}, .L[[LABEL]]73 br label %loop74loop:75 %val = call i64 @foo()76 %cond = icmp sgt i64 %val, %target77 br i1 %cond, label %loop, label %exit78exit:79 ret void80}81 82; Test SGE.83define void @f6(i64 %target) {84; CHECK-LABEL: f6:85; CHECK: .cfi_def_cfa_offset86; CHECK: .L[[LABEL:.*]]:87; CHECK: cgrjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]88 br label %loop89loop:90 %val = call i64 @foo()91 %cond = icmp sge i64 %val, %target92 br i1 %cond, label %loop, label %exit93exit:94 ret void95}96 97; Test a vector of 0/-1 results for i32 EQ.98define i64 @f7(i64 %a, i64 %b) {99; CHECK-LABEL: f7:100; CHECK: ipm [[REG:%r[0-5]]]101; CHECK: afi [[REG]], -268435456102; CHECK: sra [[REG]], 31103; CHECK: br %r14104 %avec = bitcast i64 %a to <2 x i32>105 %bvec = bitcast i64 %b to <2 x i32>106 %cmp = icmp eq <2 x i32> %avec, %bvec107 %ext = sext <2 x i1> %cmp to <2 x i32>108 %ret = bitcast <2 x i32> %ext to i64109 ret i64 %ret110}111 112; Test a vector of 0/-1 results for i32 NE.113define i64 @f8(i64 %a, i64 %b) {114; CHECK-LABEL: f8:115; CHECK: ipm [[REG:%r[0-5]]]116; CHECK: afi [[REG]], 1879048192117; CHECK: sra [[REG]], 31118; CHECK: br %r14119 %avec = bitcast i64 %a to <2 x i32>120 %bvec = bitcast i64 %b to <2 x i32>121 %cmp = icmp ne <2 x i32> %avec, %bvec122 %ext = sext <2 x i1> %cmp to <2 x i32>123 %ret = bitcast <2 x i32> %ext to i64124 ret i64 %ret125}126 127; Test a vector of 0/-1 results for i64 EQ.128define void @f9(i64 %a, i64 %b, ptr %dest) {129; CHECK-LABEL: f9:130; CHECK: ipm [[REG:%r[0-5]]]131; CHECK: afi [[REG]], -268435456132; CHECK: sllg [[REG2:%r[0-5]]], [[REG]], 32133; CHECK: srag {{%r[0-5]}}, [[REG2]], 63134; CHECK: br %r14135 %avec = bitcast i64 %a to <2 x i32>136 %bvec = bitcast i64 %b to <2 x i32>137 %cmp = icmp eq <2 x i32> %avec, %bvec138 %ext = sext <2 x i1> %cmp to <2 x i64>139 store <2 x i64> %ext, ptr %dest140 ret void141}142 143; Test a vector of 0/-1 results for i64 NE.144define void @f10(i64 %a, i64 %b, ptr %dest) {145; CHECK-LABEL: f10:146; CHECK: ipm [[REG:%r[0-5]]]147; CHECK: afi [[REG]], 1879048192148; CHECK: sllg [[REG2:%r[0-5]]], [[REG]], 32149; CHECK: srag {{%r[0-5]}}, [[REG2]], 63150; CHECK: br %r14151 %avec = bitcast i64 %a to <2 x i32>152 %bvec = bitcast i64 %b to <2 x i32>153 %cmp = icmp ne <2 x i32> %avec, %bvec154 %ext = sext <2 x i1> %cmp to <2 x i64>155 store <2 x i64> %ext, ptr %dest156 ret void157}158