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1; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck %s2 3; CHECK-LABEL: sum_vecs04; CHECK: vag 24,24,255define <2 x i64> @sum_vecs0(<2 x i64> %v1, <2 x i64> %v2) {6entry:7 %add0 = add <2 x i64> %v1, %v28 ret <2 x i64> %add09}10 11; CHECK-LABEL: sum_vecs112; CHECK: vaf 1,24,2513; CHECK: vaf 1,1,2614; CHECK: vaf 1,1,2715; CHECK: vaf 1,1,2816; CHECK: vaf 1,1,2917; CHECK: vl 0,2304(4),418; CHECK: vaf 1,1,3019; CHECK: vaf 1,1,3120; CHECK: vaf 24,1,021define <4 x i32> @sum_vecs1(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7, <4 x i32> %v8, <4 x i32> %v9) {22entry:23 %add0 = add <4 x i32> %v1, %v224 %add1 = add <4 x i32> %add0, %v325 %add2 = add <4 x i32> %add1, %v426 %add3 = add <4 x i32> %add2, %v527 %add4 = add <4 x i32> %add3, %v628 %add5 = add <4 x i32> %add4, %v729 %add6 = add <4 x i32> %add5, %v830 %add7 = add <4 x i32> %add6, %v931 ret <4 x i32> %add732}33 34; Verify that 3 is used for passing integral types if35; only 24 is used.36; CHECK-LABEL: call_vecs037; CHECK: lgr 3,138define i64 @call_vecs0(i64 %n, <2 x i64> %v1) {39entry:40 %ret = call i64 (<2 x i64>, i64) @pass_vecs0(<2 x i64> %v1, i64 %n)41 ret i64 %ret42}43 44; Verify that 3 is not allocated for passing integral types45; if 24 and %f0 are used.46; CHECK-LABEL: call_vecs147; CHECK: vlr 24,2548; CHECK: stg 1,2200(4)49define i64 @call_vecs1(i64 %n, <2 x i64> %v1, double %x, <2 x i64> %v2) {50entry:51 %ret = call i64 (<2 x i64>, double, i64) @pass_vecs1(<2 x i64> %v2, double %x, i64 %n)52 ret i64 %ret53}54 55; Verify that 3 is not allocated for passing integral types56; if 24 and 25 are used.57; CHECK-LABEL: call_vecs258; CHECK: mvghi 2208(4),5559define i64 @call_vecs2(<2 x i64> %v1, <2 x i64> %v2) {60 %ret = call i64 (<2 x i64>, <2 x i64>, i64) @pass_vecs2(<2 x i64> %v1, <2 x i64> %v2, i64 55)61 ret i64 %ret62}63 64declare i64 @pass_vecs0(<2 x i64> %v1, i64 %n)65declare i64 @pass_vecs1(<2 x i64> %v1, double %x, i64 %n)66declare i64 @pass_vecs2(<2 x i64> %v1, <2 x i64> %v2, i64 %n)67