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1# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -start-before=greedy %s -o - \2# RUN: | FileCheck %s3#4# Test that regalloc manages (via regalloc hints) to avoid a LOCRMux jump5# sequence expansion, and a SELR/LOCR instuction is emitted.6 7--- |8 ; ModuleID = 'tc.ll'9 source_filename = "tc.ll"10 target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"11 12 @globvar = external global i3213 14 declare void @fun() #015 16 define void @fun1() #0 {17 bb5:18 br label %bb619 20 bb6: ; preds = %bb33, %bb521 %tmp = phi i1 [ %tmp34, %bb33 ], [ undef, %bb5 ]22 br label %bb723 24 bb7: ; preds = %bb7, %bb625 %lsr.iv1 = phi ptr [ %0, %bb7 ], [ undef, %bb6 ]26 %tmp8 = phi i32 [ %tmp27, %bb7 ], [ -1000000, %bb6 ]27 %tmp9 = phi i64 [ %tmp28, %bb7 ], [ 0, %bb6 ]28 %lsr3 = trunc i64 %tmp9 to i3229 %lsr.iv12 = bitcast ptr %lsr.iv1 to ptr30 %tmp11 = load i32, ptr %lsr.iv1231 %tmp12 = icmp sgt i32 %tmp11, undef32 %tmp13 = trunc i64 %tmp9 to i3233 %tmp14 = select i1 %tmp12, i32 %lsr3, i32 034 %tmp15 = select i1 %tmp12, i32 %tmp13, i32 %tmp835 %tmp16 = load i32, ptr undef36 %tmp17 = select i1 false, i32 undef, i32 %tmp1437 %tmp18 = select i1 false, i32 undef, i32 %tmp1538 %tmp19 = select i1 false, i32 %tmp16, i32 undef39 %tmp20 = select i1 undef, i32 undef, i32 %tmp1740 %tmp21 = select i1 undef, i32 undef, i32 %tmp1841 %tmp22 = select i1 undef, i32 undef, i32 %tmp1942 %tmp23 = or i64 %tmp9, 343 %tmp24 = icmp sgt i32 undef, %tmp2244 %tmp25 = trunc i64 %tmp23 to i3245 %tmp26 = select i1 %tmp24, i32 %tmp25, i32 %tmp2046 %tmp27 = select i1 %tmp24, i32 %tmp25, i32 %tmp2147 %tmp28 = add nuw nsw i64 %tmp9, 448 %tmp29 = icmp eq i64 undef, 049 %scevgep = getelementptr [512 x i32], ptr %lsr.iv1, i64 0, i64 450 %0 = bitcast ptr %scevgep to ptr51 br i1 %tmp29, label %bb30, label %bb752 53 bb30: ; preds = %bb754 %tmp32 = icmp sgt i32 %tmp27, -100000055 br i1 %tmp32, label %bb33, label %bb3556 57 bb33: ; preds = %bb3058 call void @fun()59 store i32 %tmp26, ptr @globvar60 %tmp34 = icmp ugt i32 undef, 161 br label %bb662 63 bb35: ; preds = %bb3064 br i1 %tmp, label %bb37, label %bb3865 66 bb37: ; preds = %bb3567 unreachable68 69 bb38: ; preds = %bb3570 unreachable71 }72 73 ; Function Attrs: nounwind74 declare void @llvm.stackprotector(ptr, ptr) #175 76 attributes #0 = { "target-cpu"="z15" }77 attributes #1 = { nounwind }78 79...80 81# CHECK: locr82# CHECK-NOT: risblg83 84---85name: fun186alignment: 1687tracksRegLiveness: true88registers:89 - { id: 0, class: grx32bit }90 - { id: 1, class: addr64bit }91 - { id: 2, class: grx32bit }92 - { id: 3, class: addr64bit }93 - { id: 4, class: gr32bit }94 - { id: 5, class: grx32bit }95 - { id: 6, class: gr64bit }96 - { id: 7, class: gr64bit }97 - { id: 8, class: grx32bit }98 - { id: 9, class: grx32bit }99 - { id: 10, class: gr64bit }100 - { id: 11, class: grx32bit }101 - { id: 12, class: gr64bit }102 - { id: 13, class: grx32bit }103 - { id: 14, class: gr32bit }104 - { id: 15, class: gr32bit }105 - { id: 16, class: grx32bit }106 - { id: 17, class: grx32bit }107 - { id: 18, class: gr32bit }108 - { id: 19, class: addr64bit }109 - { id: 20, class: grx32bit }110 - { id: 21, class: gr32bit }111 - { id: 22, class: gr64bit }112 - { id: 23, class: grx32bit }113 - { id: 24, class: grx32bit }114 - { id: 25, class: grx32bit }115 - { id: 26, class: addr64bit }116 - { id: 27, class: grx32bit }117 - { id: 28, class: addr64bit }118frameInfo:119 adjustsStack: true120 hasCalls: true121body: |122 bb.0.bb5:123 %25:grx32bit = IMPLICIT_DEF124 125 bb.1.bb6:126 %28:addr64bit = LGHI 0127 %27:grx32bit = IIFMux 4293967296128 %26:addr64bit = IMPLICIT_DEF129 130 bb.2.bb7:131 successors: %bb.3(0x04000000), %bb.2(0x7c000000)132 133 %14:gr32bit = LMux %26, 0, $noreg :: (load (s32) from %ir.lsr.iv12)134 CR %14, undef %15:gr32bit, implicit-def $cc135 %16:grx32bit = COPY %28.subreg_l32136 %16:grx32bit = LOCHIMux %16, 0, 14, 12, implicit $cc137 %17:grx32bit = SELRMux %27, %28.subreg_l32, 14, 2, implicit killed $cc138 %18:gr32bit = LMux undef %19:addr64bit, 0, $noreg :: (load (s32) from `ptr undef`)139 %20:grx32bit = COPY %28.subreg_l32140 %20:grx32bit = OILMux %20, 3, implicit-def dead $cc141 CR undef %21:gr32bit, %18, implicit-def $cc142 %4:gr32bit = SELRMux %16, %20, 14, 2, implicit $cc143 %27:grx32bit = SELRMux %17, %20, 14, 2, implicit killed $cc144 %28:addr64bit = nuw nsw LA %28, 4, $noreg145 %26:addr64bit = LA %26, 16, $noreg146 CGHI undef %22:gr64bit, 0, implicit-def $cc147 BRC 14, 6, %bb.2, implicit killed $cc148 J %bb.3149 150 bb.3.bb30:151 successors: %bb.4(0x7fffffff), %bb.5(0x00000001)152 153 CFIMux %27, -999999, implicit-def $cc154 BRC 14, 4, %bb.5, implicit killed $cc155 J %bb.4156 157 bb.4.bb33:158 CallBRASL @fun, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc159 STRL %4, @globvar :: (store (s32) into @globvar)160 CLFIMux undef %23:grx32bit, 1, implicit-def $cc161 %25:grx32bit = LHIMux 0162 %25:grx32bit = LOCHIMux %25, 1, 14, 2, implicit killed $cc163 J %bb.1164 165 bb.5.bb35:166 successors: %bb.6, %bb.7167 168 TMLMux %25, 1, implicit-def $cc169 BRC 15, 8, %bb.7, implicit killed $cc170 J %bb.6171 172 bb.6.bb37:173 successors:174 175 176 bb.7.bb38:177 178...179