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1# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=greedy %s -o - \2# RUN: | FileCheck %s3#4# Test that the reg alloc hints are given in a good order that gives no more5# than 5 LGRs in output.6 7--- |8 ; ModuleID = 'tc.ll'9 source_filename = "tc.ll"10 target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"11 target triple = "s390x-unknown-linux-gnu"12 13 %0 = type { i32, i32, i32, float, float, float, ptr, i32 }14 15 define void @fun(i32 signext %arg, i32 zeroext %arg1) #0 {16 bb:17 %tmp = sext i32 %arg to i6418 %tmp2 = tail call ptr @sre_malloc()19 %tmp4 = tail call ptr @sre_malloc()20 %tmp6 = add i32 %arg, -121 tail call void @malloc()22 %0 = trunc i32 %arg to i223 %1 = add i2 %0, -124 br label %bb825 26 bb8: ; preds = %bb54, %bb27 %lsr.iv6 = phi i2 [ %lsr.iv.next7, %bb54 ], [ %1, %bb ]28 %tmp9 = phi i64 [ %tmp57, %bb54 ], [ 0, %bb ]29 %tmp10 = phi i64 [ 0, %bb54 ], [ %tmp, %bb ]30 %tmp12 = sub i64 %tmp, %tmp931 br label %bb1432 33 bb14: ; preds = %bb39, %bb834 %lsr.iv8 = phi i2 [ %lsr.iv.next9, %bb39 ], [ %lsr.iv6, %bb8 ]35 %lsr.iv = phi i32 [ %lsr.iv.next, %bb39 ], [ 1, %bb8 ]36 %tmp15 = phi i64 [ 0, %bb8 ], [ %tmp19, %bb39 ]37 %tmp17 = phi i32 [ %tmp6, %bb8 ], [ %tmp35, %bb39 ]38 %tmp18 = phi i32 [ 0, %bb8 ], [ %tmp34, %bb39 ]39 %2 = bitcast ptr %tmp2 to ptr40 %tmp19 = add nuw nsw i64 %tmp15, 141 %3 = zext i2 %lsr.iv8 to i6442 %4 = mul i64 %3, -143 %tmp21 = getelementptr inbounds ptr, ptr %2, i64 %tmp1544 %tmp22 = load ptr, ptr %tmp2145 %tmp23 = trunc i64 %tmp15 to i3246 %scevgep = getelementptr float, ptr %tmp22, i64 %tmp1547 br label %bb2548 49 bb25: ; preds = %bb25, %bb1450 %lsr.iv10 = phi i64 [ %lsr.iv.next11, %bb25 ], [ %4, %bb14 ]51 %lsr.iv3 = phi ptr [ %scevgep4, %bb25 ], [ %scevgep, %bb14 ]52 %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb25 ], [ %lsr.iv, %bb14 ]53 %tmp27 = phi i32 [ %tmp35, %bb25 ], [ %tmp17, %bb14 ]54 %tmp28 = phi i32 [ %tmp34, %bb25 ], [ %tmp18, %bb14 ]55 %scevgep5 = getelementptr float, ptr %lsr.iv3, i64 156 %tmp31 = load float, ptr %scevgep557 %tmp32 = fcmp olt float %tmp31, undef58 %tmp34 = select i1 %tmp32, i32 %lsr.iv1, i32 %tmp2859 %tmp35 = select i1 %tmp32, i32 %tmp23, i32 %tmp2760 %lsr.iv.next2 = add i32 %lsr.iv1, 161 %scevgep4 = getelementptr float, ptr %lsr.iv3, i64 162 %lsr.iv.next11 = add i64 %lsr.iv10, 163 %tmp38 = icmp eq i64 %lsr.iv.next11, 064 br i1 %tmp38, label %bb39, label %bb2565 66 bb39: ; preds = %bb2567 %lsr.iv.next = add i32 %lsr.iv, 168 %lsr.iv.next9 = add i2 %lsr.iv8, -169 %tmp41 = icmp eq i64 %tmp19, %tmp1070 br i1 %tmp41, label %bb42, label %bb1471 72 bb42: ; preds = %bb3973 %5 = bitcast ptr %tmp4 to ptr74 %tmp43 = getelementptr inbounds i32, ptr %5, i64 undef75 %tmp44 = load i32, ptr %tmp4376 %tmp45 = sub nsw i32 %tmp44, %arg77 %tmp46 = sext i32 %tmp45 to i6478 %tmp47 = getelementptr inbounds %0, ptr null, i64 %tmp46, i32 779 %tmp48 = load i32, ptr %tmp4780 %tmp49 = add nsw i32 0, %tmp4881 store i32 %tmp49, ptr undef82 %cond = icmp eq i32 %arg1, 083 br i1 %cond, label %bb52, label %bb5484 85 bb52: ; preds = %bb4286 %tmp5312 = bitcast ptr undef to ptr87 br label %bb5488 89 bb54: ; preds = %bb42, %bb5290 %6 = bitcast ptr %tmp4 to ptr91 %tmp55 = add i32 0, %arg92 %tmp56 = getelementptr inbounds i32, ptr %6, i64 undef93 store i32 %tmp55, ptr %tmp5694 %tmp57 = add i64 %tmp9, 195 %lsr.iv.next7 = add i2 %lsr.iv6, -196 br label %bb897 }98 99 declare ptr @sre_malloc() #0100 101 declare void @malloc() #0102 103 ; Function Attrs: nounwind104 declare void @llvm.stackprotector(ptr, ptr) #1105 106 attributes #0 = { "target-cpu"="z13" }107 attributes #1 = { nounwind }108 109...110 111# CHECK: lgr112# CHECK: lgr113# CHECK: lgr114# CHECK: lgr115# CHECK: lgr116# CHECK-NOT: lgr117 118---119name: fun120alignment: 16121tracksRegLiveness: true122registers: 123 - { id: 0, class: gr64bit }124 - { id: 1, class: addr64bit }125 - { id: 2, class: addr64bit }126 - { id: 3, class: gr32bit }127 - { id: 4, class: gr32bit }128 - { id: 5, class: grx32bit }129 - { id: 6, class: addr64bit }130 - { id: 7, class: gr64bit }131 - { id: 8, class: grx32bit }132 - { id: 9, class: grx32bit }133 - { id: 10, class: addr64bit }134 - { id: 11, class: grx32bit }135 - { id: 12, class: grx32bit }136 - { id: 13, class: gr64bit }137 - { id: 14, class: gr64bit }138 - { id: 15, class: grx32bit }139 - { id: 16, class: gr64bit }140 - { id: 17, class: addr64bit }141 - { id: 18, class: addr64bit }142 - { id: 19, class: grx32bit }143 - { id: 20, class: grx32bit }144 - { id: 21, class: grx32bit }145 - { id: 22, class: grx32bit }146 - { id: 23, class: grx32bit }147 - { id: 24, class: grx32bit }148 - { id: 25, class: gr64bit }149 - { id: 26, class: gr64bit }150 - { id: 27, class: grx32bit }151 - { id: 28, class: grx32bit }152 - { id: 29, class: gr64bit }153 - { id: 30, class: grx32bit }154 - { id: 31, class: gr64bit }155 - { id: 32, class: gr64bit }156 - { id: 33, class: gr32bit }157 - { id: 34, class: grx32bit }158 - { id: 35, class: gr64bit }159 - { id: 36, class: gr64bit }160 - { id: 37, class: gr64bit }161 - { id: 38, class: grx32bit }162 - { id: 39, class: gr64bit }163 - { id: 40, class: grx32bit }164 - { id: 41, class: gr64bit }165 - { id: 42, class: gr64bit }166 - { id: 43, class: gr64bit }167 - { id: 44, class: gr64bit }168 - { id: 45, class: addr64bit }169 - { id: 46, class: gr64bit }170 - { id: 47, class: fp32bit }171 - { id: 48, class: fp32bit }172 - { id: 49, class: gr32bit }173 - { id: 50, class: gr32bit }174 - { id: 51, class: gr64bit }175 - { id: 52, class: addr64bit }176 - { id: 53, class: addr64bit }177 - { id: 54, class: gr64bit }178 - { id: 55, class: gr32bit }179 - { id: 56, class: addr64bit }180 - { id: 57, class: gr64bit }181 - { id: 58, class: grx32bit }182 - { id: 59, class: grx32bit }183 - { id: 60, class: addr64bit }184 - { id: 61, class: grx32bit }185 - { id: 62, class: grx32bit }186 - { id: 63, class: addr64bit }187 - { id: 64, class: addr64bit }188 - { id: 65, class: grx32bit }189 - { id: 66, class: grx32bit }190 - { id: 67, class: grx32bit }191liveins: 192 - { reg: '$r2d', virtual-reg: '%31' }193 - { reg: '$r3d', virtual-reg: '%32' }194frameInfo: 195 adjustsStack: true196 hasCalls: true197body: |198 bb.0.bb:199 liveins: $r2d, $r3d200 201 %32:gr64bit = COPY $r3d202 %0:gr64bit = COPY $r2d203 CallBRASL @sre_malloc, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $r2d204 %1:addr64bit = COPY $r2d205 CallBRASL @sre_malloc, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $r2d206 %2:addr64bit = COPY $r2d207 %3:gr32bit = AHIMuxK %0.subreg_l32, -1, implicit-def dead $cc208 CallBRASL @malloc, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc209 %55:gr32bit = AHIMuxK %0.subreg_l32, 3, implicit-def dead $cc210 %56:addr64bit = LGHI 0211 %57:gr64bit = COPY %0212 213 bb.1.bb8:214 %62:grx32bit = LHIMux 0215 %59:grx32bit = LHIMux 1216 undef %41.subreg_l32:gr64bit = COPY %55217 %60:addr64bit = LGHI 0218 %61:grx32bit = COPY %3219 220 bb.2.bb14:221 %10:addr64bit = COPY %60222 %60:addr64bit = nuw nsw LA %10, 1, $noreg223 %43:gr64bit = RISBGN undef %43, %41, 62, 191, 0224 %63:addr64bit = LCGR %43, implicit-def dead $cc225 %45:addr64bit = SLLG %10, $noreg, 3226 %64:addr64bit = SLLG %10, $noreg, 2227 %64:addr64bit = AG %64, %1, 0, %45, implicit-def dead $cc :: (load (s64) from %ir.tmp21)228 %65:grx32bit = COPY %59229 230 bb.3.bb25:231 successors: %bb.4(0x04000000), %bb.3(0x7c000000)232 233 %47:fp32bit = VL32 %64, 4, $noreg :: (load (s32) from %ir.scevgep5)234 %25:gr64bit = LA %64, 4, $noreg235 CEBR %47, undef %48:fp32bit, implicit-def $cc, implicit $fpc236 %62:grx32bit = LOCRMux %62, %65, 15, 4, implicit $cc237 %61:grx32bit = LOCRMux %61, %10.subreg_l32, 15, 4, implicit killed $cc238 %65:grx32bit = AHIMux %65, 1, implicit-def dead $cc239 %63:addr64bit = LA %63, 1, $noreg240 CGHI %63, 0, implicit-def $cc241 %64:addr64bit = COPY %25242 BRC 14, 6, %bb.3, implicit killed $cc243 J %bb.4244 245 bb.4.bb39:246 successors: %bb.5(0x04000000), %bb.2(0x7c000000)247 248 %59:grx32bit = AHIMux %59, 1, implicit-def dead $cc249 %41.subreg_l32:gr64bit = AHIMux %41.subreg_l32, 3, implicit-def dead $cc250 CGR %60, %57, implicit-def $cc251 BRC 14, 6, %bb.2, implicit killed $cc252 J %bb.5253 254 bb.5.bb42:255 successors: %bb.6(0x30000000), %bb.7(0x50000000)256 257 %50:gr32bit = LMux %2, 0, $noreg :: (load (s32) from %ir.tmp43)258 %50:gr32bit = nsw SR %50, %0.subreg_l32, implicit-def dead $cc259 %52:addr64bit = LGFR %50260 %52:addr64bit = MGHI %52, 40261 MVC undef %53:addr64bit, 0, 4, %52, 32 :: (store (s32) into `ptr undef`), (load (s32) from %ir.tmp47)262 CHIMux %32.subreg_l32, 0, implicit-def $cc263 BRC 14, 6, %bb.7, implicit killed $cc264 J %bb.6265 266 bb.6.bb52:267 268 bb.7.bb54:269 STMux %0.subreg_l32, %2, 0, $noreg :: (store (s32) into %ir.tmp56)270 %56:addr64bit = LA %56, 1, $noreg271 %55:gr32bit = AHIMux %55, 3, implicit-def dead $cc272 %57:gr64bit = LGHI 0273 J %bb.1274 275...276