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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=NO-MISC33; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s --check-prefix=MISC34 5; test that masked-merge code is generated as "xor;and;xor" sequence or6; "andn ; and; or" if and-not is available.7 8define i32 @masked_merge0(i32 %a0, i32 %a1, i32 %a2) {9; NO-MISC3-LABEL: masked_merge0:10; NO-MISC3: # %bb.0:11; NO-MISC3-NEXT: xr %r3, %r412; NO-MISC3-NEXT: nr %r2, %r313; NO-MISC3-NEXT: xr %r2, %r414; NO-MISC3-NEXT: br %r1415;16; MISC3-LABEL: masked_merge0:17; MISC3: # %bb.0:18; MISC3-NEXT: nr %r3, %r219; MISC3-NEXT: ncrk %r2, %r4, %r220; MISC3-NEXT: or %r2, %r321; MISC3-NEXT: br %r1422 %and0 = and i32 %a0, %a123 %not = xor i32 %a0, -124 %and1 = and i32 %not, %a225 %or = or i32 %and0, %and126 ret i32 %or27}28 29define i16 @masked_merge1(i16 %a0, i16 %a1, i16 %a2) {30; NO-MISC3-LABEL: masked_merge1:31; NO-MISC3: # %bb.0:32; NO-MISC3-NEXT: xr %r3, %r433; NO-MISC3-NEXT: nr %r2, %r334; NO-MISC3-NEXT: xr %r2, %r435; NO-MISC3-NEXT: br %r1436;37; MISC3-LABEL: masked_merge1:38; MISC3: # %bb.0:39; MISC3-NEXT: ncrk %r0, %r4, %r240; MISC3-NEXT: nr %r2, %r341; MISC3-NEXT: or %r2, %r042; MISC3-NEXT: br %r1443 %and0 = and i16 %a0, %a144 %not = xor i16 %a0, -145 %and1 = and i16 %a2, %not46 %or = or i16 %and0, %and147 ret i16 %or48}49 50define i8 @masked_merge2(i8 %a0, i8 %a1, i8 %a2) {51; NO-MISC3-LABEL: masked_merge2:52; NO-MISC3: # %bb.0:53; NO-MISC3-NEXT: lr %r2, %r354; NO-MISC3-NEXT: br %r1455;56; MISC3-LABEL: masked_merge2:57; MISC3: # %bb.0:58; MISC3-NEXT: lr %r2, %r359; MISC3-NEXT: br %r1460 %not = xor i8 %a0, -161 %and0 = and i8 %not, %a162 %and1 = and i8 %a1, %a063 %or = or i8 %and0, %and164 ret i8 %or65}66 67define i64 @masked_merge3(i64 %a0, i64 %a1, i64 %a2) {68; NO-MISC3-LABEL: masked_merge3:69; NO-MISC3: # %bb.0:70; NO-MISC3-NEXT: lcgr %r0, %r471; NO-MISC3-NEXT: aghi %r0, -172; NO-MISC3-NEXT: xgr %r3, %r073; NO-MISC3-NEXT: ngr %r3, %r274; NO-MISC3-NEXT: xgr %r3, %r275; NO-MISC3-NEXT: xgrk %r2, %r3, %r076; NO-MISC3-NEXT: br %r1477;78; MISC3-LABEL: masked_merge3:79; MISC3: # %bb.0:80; MISC3-NEXT: lcgr %r0, %r281; MISC3-NEXT: aghi %r0, -182; MISC3-NEXT: ncgrk %r0, %r0, %r483; MISC3-NEXT: ncgrk %r2, %r2, %r384; MISC3-NEXT: ogr %r2, %r085; MISC3-NEXT: br %r1486 %v0 = xor i64 %a1, -187 %v1 = xor i64 %a2, -188 %not = xor i64 %a0, -189 %and0 = and i64 %not, %v190 %and1 = and i64 %v0, %a091 %or = or i64 %and0, %and192 ret i64 %or93}94 95define i32 @not_a_masked_merge0(i32 %a0, i32 %a1, i32 %a2) {96; NO-MISC3-LABEL: not_a_masked_merge0:97; NO-MISC3: # %bb.0:98; NO-MISC3-NEXT: lcr %r0, %r299; NO-MISC3-NEXT: nr %r3, %r2100; NO-MISC3-NEXT: nr %r0, %r4101; NO-MISC3-NEXT: ork %r2, %r3, %r0102; NO-MISC3-NEXT: br %r14103;104; MISC3-LABEL: not_a_masked_merge0:105; MISC3: # %bb.0:106; MISC3-NEXT: lcr %r0, %r2107; MISC3-NEXT: nr %r3, %r2108; MISC3-NEXT: nr %r0, %r4109; MISC3-NEXT: ork %r2, %r3, %r0110; MISC3-NEXT: br %r14111 %and0 = and i32 %a0, %a1112 %not_a_not = sub i32 0, %a0113 %and1 = and i32 %not_a_not, %a2114 %or = or i32 %and0, %and1115 ret i32 %or116}117 118define i32 @not_a_masked_merge1(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {119; NO-MISC3-LABEL: not_a_masked_merge1:120; NO-MISC3: # %bb.0:121; NO-MISC3-NEXT: xilf %r5, 4294967295122; NO-MISC3-NEXT: nr %r2, %r3123; NO-MISC3-NEXT: nr %r4, %r5124; NO-MISC3-NEXT: or %r2, %r4125; NO-MISC3-NEXT: br %r14126;127; MISC3-LABEL: not_a_masked_merge1:128; MISC3: # %bb.0:129; MISC3-NEXT: nr %r2, %r3130; MISC3-NEXT: ncrk %r0, %r4, %r5131; MISC3-NEXT: or %r2, %r0132; MISC3-NEXT: br %r14133 %and0 = and i32 %a0, %a1134 %not = xor i32 %a3, -1135 %and1 = and i32 %not, %a2136 %or = or i32 %and0, %and1137 ret i32 %or138}139 140define i32 @not_a_masked_merge2(i32 %a0, i32 %a1, i32 %a2) {141; NO-MISC3-LABEL: not_a_masked_merge2:142; NO-MISC3: # %bb.0:143; NO-MISC3-NEXT: or %r3, %r2144; NO-MISC3-NEXT: xilf %r2, 4294967295145; NO-MISC3-NEXT: nr %r2, %r4146; NO-MISC3-NEXT: or %r2, %r3147; NO-MISC3-NEXT: br %r14148;149; MISC3-LABEL: not_a_masked_merge2:150; MISC3: # %bb.0:151; MISC3-NEXT: or %r3, %r2152; MISC3-NEXT: ncrk %r2, %r4, %r2153; MISC3-NEXT: or %r2, %r3154; MISC3-NEXT: br %r14155 %not_an_and0 = or i32 %a0, %a1156 %not = xor i32 %a0, -1157 %and1 = and i32 %not, %a2158 %or = or i32 %not_an_and0, %and1159 ret i32 %or160}161 162define i32 @not_a_masked_merge3(i32 %a0, i32 %a1, i32 %a2) {163; NO-MISC3-LABEL: not_a_masked_merge3:164; NO-MISC3: # %bb.0:165; NO-MISC3-NEXT: nr %r3, %r2166; NO-MISC3-NEXT: xr %r2, %r4167; NO-MISC3-NEXT: xilf %r2, 4294967295168; NO-MISC3-NEXT: or %r2, %r3169; NO-MISC3-NEXT: br %r14170;171; MISC3-LABEL: not_a_masked_merge3:172; MISC3: # %bb.0:173; MISC3-NEXT: nr %r3, %r2174; MISC3-NEXT: xr %r2, %r4175; MISC3-NEXT: ocrk %r2, %r3, %r2176; MISC3-NEXT: br %r14177 %and0 = and i32 %a0, %a1178 %not = xor i32 %a0, -1179 %not_an_and1 = xor i32 %not, %a2180 %or = or i32 %and0, %not_an_and1181 ret i32 %or182}183 184define i32 @not_a_masked_merge4(i32 %a0, i32 %a1, i32 %a2) {185; NO-MISC3-LABEL: not_a_masked_merge4:186; NO-MISC3: # %bb.0:187; NO-MISC3-NEXT: nr %r2, %r3188; NO-MISC3-NEXT: br %r14189;190; MISC3-LABEL: not_a_masked_merge4:191; MISC3: # %bb.0:192; MISC3-NEXT: nr %r2, %r3193; MISC3-NEXT: br %r14194 %and0 = and i32 %a0, %a1195 %not = xor i32 %a2, -1196 %and1 = and i32 %not, %a2197 %or = or i32 %and0, %and1198 ret i32 %or199}200 201define i32 @masked_merge_no_transform0(i32 %a0, i32 %a1, i32 %a2, ptr %p1) {202; NO-MISC3-LABEL: masked_merge_no_transform0:203; NO-MISC3: # %bb.0:204; NO-MISC3-NEXT: nr %r3, %r2205; NO-MISC3-NEXT: xilf %r2, 4294967295206; NO-MISC3-NEXT: nr %r2, %r4207; NO-MISC3-NEXT: or %r2, %r3208; NO-MISC3-NEXT: st %r3, 0(%r5)209; NO-MISC3-NEXT: br %r14210;211; MISC3-LABEL: masked_merge_no_transform0:212; MISC3: # %bb.0:213; MISC3-NEXT: nr %r3, %r2214; MISC3-NEXT: ncrk %r2, %r4, %r2215; MISC3-NEXT: or %r2, %r3216; MISC3-NEXT: st %r3, 0(%r5)217; MISC3-NEXT: br %r14218 %and0 = and i32 %a0, %a1219 %not = xor i32 %a0, -1220 %and1 = and i32 %not, %a2221 %or = or i32 %and0, %and1222 store i32 %and0, ptr %p1223 ret i32 %or224}225 226define i32 @masked_merge_no_transform1(i32 %a0, i32 %a1, i32 %a2, ptr %p1) {227; NO-MISC3-LABEL: masked_merge_no_transform1:228; NO-MISC3: # %bb.0:229; NO-MISC3-NEXT: nrk %r0, %r2, %r3230; NO-MISC3-NEXT: xilf %r2, 4294967295231; NO-MISC3-NEXT: nr %r4, %r2232; NO-MISC3-NEXT: or %r0, %r4233; NO-MISC3-NEXT: st %r2, 0(%r5)234; NO-MISC3-NEXT: lr %r2, %r0235; NO-MISC3-NEXT: br %r14236;237; MISC3-LABEL: masked_merge_no_transform1:238; MISC3: # %bb.0:239; MISC3-NEXT: nrk %r0, %r2, %r3240; MISC3-NEXT: ncrk %r1, %r4, %r2241; MISC3-NEXT: xilf %r2, 4294967295242; MISC3-NEXT: or %r0, %r1243; MISC3-NEXT: st %r2, 0(%r5)244; MISC3-NEXT: lr %r2, %r0245; MISC3-NEXT: br %r14246 %and0 = and i32 %a0, %a1247 %not = xor i32 %a0, -1248 %and1 = and i32 %not, %a2249 %or = or i32 %and0, %and1250 store i32 %not, ptr %p1251 ret i32 %or252}253 254define i32 @masked_merge_no_transform2(i32 %a0, i32 %a1, i32 %a2, ptr %p1) {255; NO-MISC3-LABEL: masked_merge_no_transform2:256; NO-MISC3: # %bb.0:257; NO-MISC3-NEXT: nr %r3, %r2258; NO-MISC3-NEXT: xilf %r2, 4294967295259; NO-MISC3-NEXT: nr %r4, %r2260; NO-MISC3-NEXT: ork %r2, %r3, %r4261; NO-MISC3-NEXT: st %r4, 0(%r5)262; NO-MISC3-NEXT: br %r14263;264; MISC3-LABEL: masked_merge_no_transform2:265; MISC3: # %bb.0:266; MISC3-NEXT: nr %r3, %r2267; MISC3-NEXT: ncrk %r0, %r4, %r2268; MISC3-NEXT: ork %r2, %r3, %r0269; MISC3-NEXT: st %r0, 0(%r5)270; MISC3-NEXT: br %r14271 %and0 = and i32 %a0, %a1272 %not = xor i32 %a0, -1273 %and1 = and i32 %not, %a2274 %or = or i32 %and0, %and1275 store i32 %and1, ptr %p1276 ret i32 %or277}278