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1; Test 32-bit floating-point addition.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \4; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s6 7declare float @foo()8 9; Check register addition.10define half @f0(half %f1, half %f2) {11; CHECK-LABEL: f0:12; CHECK: brasl %r14, __extendhfsf2@PLT13; CHECK: brasl %r14, __extendhfsf2@PLT14; CHECK: aebr %f0, %f915; CHECK: brasl %r14, __truncsfhf2@PLT16; CHECK: br %r1417 %res = fadd half %f1, %f218 ret half %res19}20 21; Check register addition.22define float @f1(float %f1, float %f2) {23; CHECK-LABEL: f1:24; CHECK: aebr %f0, %f225; CHECK: br %r1426 %res = fadd float %f1, %f227 ret float %res28}29 30; Check the low end of the AEB range.31define float @f2(float %f1, ptr %ptr) {32; CHECK-LABEL: f2:33; CHECK: aeb %f0, 0(%r2)34; CHECK: br %r1435 %f2 = load float, ptr %ptr36 %res = fadd float %f1, %f237 ret float %res38}39 40; Check the high end of the aligned AEB range.41define float @f3(float %f1, ptr %base) {42; CHECK-LABEL: f3:43; CHECK: aeb %f0, 4092(%r2)44; CHECK: br %r1445 %ptr = getelementptr float, ptr %base, i64 102346 %f2 = load float, ptr %ptr47 %res = fadd float %f1, %f248 ret float %res49}50 51; Check the next word up, which needs separate address logic.52; Other sequences besides this one would be OK.53define float @f4(float %f1, ptr %base) {54; CHECK-LABEL: f4:55; CHECK: aghi %r2, 409656; CHECK: aeb %f0, 0(%r2)57; CHECK: br %r1458 %ptr = getelementptr float, ptr %base, i64 102459 %f2 = load float, ptr %ptr60 %res = fadd float %f1, %f261 ret float %res62}63 64; Check negative displacements, which also need separate address logic.65define float @f5(float %f1, ptr %base) {66; CHECK-LABEL: f5:67; CHECK: aghi %r2, -468; CHECK: aeb %f0, 0(%r2)69; CHECK: br %r1470 %ptr = getelementptr float, ptr %base, i64 -171 %f2 = load float, ptr %ptr72 %res = fadd float %f1, %f273 ret float %res74}75 76; Check that AEB allows indices.77define float @f6(float %f1, ptr %base, i64 %index) {78; CHECK-LABEL: f6:79; CHECK: sllg %r1, %r3, 280; CHECK: aeb %f0, 400(%r1,%r2)81; CHECK: br %r1482 %ptr1 = getelementptr float, ptr %base, i64 %index83 %ptr2 = getelementptr float, ptr %ptr1, i64 10084 %f2 = load float, ptr %ptr285 %res = fadd float %f1, %f286 ret float %res87}88 89; Check that additions of spilled values can use AEB rather than AEBR.90define float @f7(ptr %ptr0) {91; CHECK-LABEL: f7:92; CHECK: brasl %r14, foo@PLT93; CHECK-SCALAR: aeb %f0, 16{{[04]}}(%r15)94; CHECK: br %r1495 %ptr1 = getelementptr float, ptr %ptr0, i64 296 %ptr2 = getelementptr float, ptr %ptr0, i64 497 %ptr3 = getelementptr float, ptr %ptr0, i64 698 %ptr4 = getelementptr float, ptr %ptr0, i64 899 %ptr5 = getelementptr float, ptr %ptr0, i64 10100 %ptr6 = getelementptr float, ptr %ptr0, i64 12101 %ptr7 = getelementptr float, ptr %ptr0, i64 14102 %ptr8 = getelementptr float, ptr %ptr0, i64 16103 %ptr9 = getelementptr float, ptr %ptr0, i64 18104 %ptr10 = getelementptr float, ptr %ptr0, i64 20105 106 %val0 = load float, ptr %ptr0107 %val1 = load float, ptr %ptr1108 %val2 = load float, ptr %ptr2109 %val3 = load float, ptr %ptr3110 %val4 = load float, ptr %ptr4111 %val5 = load float, ptr %ptr5112 %val6 = load float, ptr %ptr6113 %val7 = load float, ptr %ptr7114 %val8 = load float, ptr %ptr8115 %val9 = load float, ptr %ptr9116 %val10 = load float, ptr %ptr10117 118 %ret = call float @foo()119 120 %add0 = fadd float %ret, %val0121 %add1 = fadd float %add0, %val1122 %add2 = fadd float %add1, %val2123 %add3 = fadd float %add2, %val3124 %add4 = fadd float %add3, %val4125 %add5 = fadd float %add4, %val5126 %add6 = fadd float %add5, %val6127 %add7 = fadd float %add6, %val7128 %add8 = fadd float %add7, %val8129 %add9 = fadd float %add8, %val9130 %add10 = fadd float %add9, %val10131 132 ret float %add10133}134 135; Check that reassociation flags do not get in the way of AEB.136define float @f8(ptr %x) {137; CHECK-LABEL: f8:138; CHECK: aeb %f0139entry:140 %0 = load float, ptr %x, align 8141 %arrayidx1 = getelementptr inbounds float, ptr %x, i64 1142 %1 = load float, ptr %arrayidx1, align 8143 %add = fadd reassoc nsz arcp contract afn float %1, %0144 ret float %add145}146