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1; Test conversions of unsigned i32s to floating-point values (z10 only).2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s4 5; Check i32->f16. There is no native instruction, so we must promote6; to i64 first.7define half @f0(i32 %i) {8; CHECK-LABEL: f0:9; CHECK: llgfr [[REGISTER:%r[0-5]]], %r210; CHECK: cegbr %f0, [[REGISTER]]11; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT12; CHECK: br %r1413 %conv = uitofp i32 %i to half14 ret half %conv15}16 17; Check i32->f32. There is no native instruction, so we must promote18; to i64 first.19define float @f1(i32 %i) {20; CHECK-LABEL: f1:21; CHECK: llgfr [[REGISTER:%r[0-5]]], %r222; CHECK: cegbr %f0, [[REGISTER]]23; CHECK: br %r1424 %conv = uitofp i32 %i to float25 ret float %conv26}27 28; Check i32->f64.29define double @f2(i32 %i) {30; CHECK-LABEL: f2:31; CHECK: llgfr [[REGISTER:%r[0-5]]], %r232; CHECK: cdgbr %f0, [[REGISTER]]33; CHECK: br %r1434 %conv = uitofp i32 %i to double35 ret double %conv36}37 38; Check i32->f128.39define void @f3(i32 %i, ptr %dst) {40; CHECK-LABEL: f3:41; CHECK: llgfr [[REGISTER:%r[0-5]]], %r242; CHECK: cxgbr %f0, [[REGISTER]]43; CHECK: std %f0, 0(%r3)44; CHECK: std %f2, 8(%r3)45; CHECK: br %r1446 %conv = uitofp i32 %i to fp12847 store fp128 %conv, ptr %dst48 ret void49}50