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1; Verify that floating-point strict signaling compares cannot be omitted2; even if CC already has the right value.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \5; RUN: -enable-misched=0 -no-integrated-as | FileCheck %s6;7; We need -enable-misched=0 to make sure f12 and following routines really8; test the compare elimination pass.9 10 11declare float @llvm.fabs.f32(float %f)12 13; Test addition followed by EQ, which could use the CC result of the addition.14define float @f1(float %a, float %b, ptr %dest) #0 {15; CHECK-LABEL: f1:16; CHECK-DAG: aebr %f0, %f217; CHECK-DAG: lzer [[REG:%f[0-9]+]]18; CHECK-NEXT: kebr %f0, [[REG]]19; CHECK-NEXT: ber %r1420; CHECK: br %r1421entry:22 %res = call float @llvm.experimental.constrained.fadd.f32(23 float %a, float %b,24 metadata !"round.dynamic",25 metadata !"fpexcept.strict") #026 %cmp = call i1 @llvm.experimental.constrained.fcmps.f32(27 float %res, float 0.0,28 metadata !"oeq",29 metadata !"fpexcept.strict") #030 br i1 %cmp, label %exit, label %store31 32store:33 store float %b, ptr %dest34 br label %exit35 36exit:37 ret float %res38}39 40; Test the result of LOAD POSITIVE.41define float @f6(float %dummy, float %a, ptr %dest) #0 {42; CHECK-LABEL: f6:43; CHECK-DAG: lpdfr %f0, %f244; CHECK-DAG: lzer [[REG:%f[0-9]+]]45; CHECK-NEXT: kebr %f0, [[REG]]46; CHECK-NEXT: bhr %r1447; CHECK: br %r1448entry:49 %res = call float @llvm.fabs.f32(float %a) #050 %cmp = call i1 @llvm.experimental.constrained.fcmps.f32(51 float %res, float 0.0,52 metadata !"ogt",53 metadata !"fpexcept.strict") #054 br i1 %cmp, label %exit, label %store55 56store:57 store float %res, ptr %dest58 br label %exit59 60exit:61 ret float %res62}63 64; Test the result of LOAD NEGATIVE.65define float @f7(float %dummy, float %a, ptr %dest) #0 {66; CHECK-LABEL: f7:67; CHECK-DAG: lndfr %f0, %f268; CHECK-DAG: lzer [[REG:%f[0-9]+]]69; CHECK-NEXT: kebr %f0, [[REG]]70; CHECK-NEXT: blr %r1471; CHECK: br %r1472entry:73 %abs = call float @llvm.fabs.f32(float %a) #074 %res = fneg float %abs75 %cmp = call i1 @llvm.experimental.constrained.fcmps.f32(76 float %res, float 0.0,77 metadata !"olt",78 metadata !"fpexcept.strict") #079 br i1 %cmp, label %exit, label %store80 81store:82 store float %res, ptr %dest83 br label %exit84 85exit:86 ret float %res87}88 89; Test the result of LOAD COMPLEMENT.90define float @f8(float %dummy, float %a, ptr %dest) #0 {91; CHECK-LABEL: f8:92; CHECK-DAG: lcdfr %f0, %f293; CHECK-DAG: lzer [[REG:%f[0-9]+]]94; CHECK-NEXT: kebr %f0, [[REG]]95; CHECK-NEXT: bler %r1496; CHECK: br %r1497entry:98 %res = fneg float %a99 %cmp = call i1 @llvm.experimental.constrained.fcmps.f32(100 float %res, float 0.0,101 metadata !"ole",102 metadata !"fpexcept.strict") #0103 br i1 %cmp, label %exit, label %store104 105store:106 store float %res, ptr %dest107 br label %exit108 109exit:110 ret float %res111}112 113define half @f12_half(half %dummy, half %val) #0 {114; CHECK-LABEL: f12_half:115; CHECK: ler %f9, %f2116; CHECK-NEXT: ler %f0, %f2117; CHECK-NEXT: #APP118; CHECK-NEXT: ler %f8, %f0119; CHECK-NEXT: #NO_APP120; CHECK-NEXT: lzer %f0121; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT122; CHECK-NEXT: ler %f10, %f0123; CHECK-NEXT: ler %f0, %f9124; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT125; CHECK-NEXT: kebr %f0, %f10126; CHECK-NEXT: jl .LBB4_2127; CHECK-NEXT:# %bb.1: # %store128; CHECK-NEXT: #APP129; CHECK-NEXT: blah130; CHECK-NEXT: #NO_APP131; CHECK-NEXT:.LBB4_2: # %exit132; CHECK-NEXT: ler %f0, %f8133; CHECK: br %r14134entry:135 %ret = call half asm "ler $0, $1", "=f,{f0}"(half %val) #0136 %cmp = call i1 @llvm.experimental.constrained.fcmps.f16(137 half %val, half 0.0,138 metadata !"olt",139 metadata !"fpexcept.strict") #0140 br i1 %cmp, label %exit, label %store141 142store:143 call void asm sideeffect "blah", ""() #0144 br label %exit145 146exit:147 ret half %ret148}149 150; Test that LER does not get converted to LTEBR.151define float @f12(float %dummy, float %val) #0 {152; CHECK-LABEL: f12:153; CHECK: ler %f0, %f2154; CHECK-NEXT: #APP155; CHECK-NEXT: blah %f0156; CHECK-NEXT: #NO_APP157; CHECK-NEXT: lzer [[REG:%f[0-9]+]]158; CHECK-NEXT: kebr %f2, [[REG]]159; CHECK-NEXT: blr %r14160; CHECK: br %r14161entry:162 %ret = call float asm "blah $1", "=f,{f0}"(float %val) #0163 %cmp = call i1 @llvm.experimental.constrained.fcmps.f32(164 float %val, float 0.0,165 metadata !"olt",166 metadata !"fpexcept.strict") #0167 br i1 %cmp, label %exit, label %store168 169store:170 call void asm sideeffect "blah", ""() #0171 br label %exit172 173exit:174 ret float %ret175}176 177attributes #0 = { strictfp }178 179declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)180declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata)181declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata)182declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata)183declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata)184declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)185declare i1 @llvm.experimental.constrained.fcmps.f128(fp128, fp128, metadata, metadata)186