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1; Test the handling of base + displacement addresses for large frames,2; in cases where both 12-bit and 20-bit displacements are allowed.3; The tests here assume z10 register pressure, without the high words4; being available.5;6; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \7; RUN: FileCheck -check-prefix=CHECK-NOFP %s8; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -frame-pointer=all | \9; RUN: FileCheck -check-prefix=CHECK-FP %s10;11; This file tests what happens when a displacement is converted from12; being relative to the start of a frame object to being relative to13; the frame itself. In some cases the test is only possible if two14; objects are allocated.15;16; Rather than rely on a particular order for those objects, the tests17; instead allocate two objects of the same size and apply the test to18; both of them. For consistency, all tests follow this model, even if19; one object would actually be enough.20 21; First check the highest offset that is in range of the 12-bit form.22;23; The last in-range doubleword offset is 4088. Since the frame has two24; emergency spill slots at 160(%r15), the amount that we need to allocate25; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.26define void @f1() {27; CHECK-NOFP-LABEL: f1:28; CHECK-NOFP: mvi 4095(%r15), 4229; CHECK-NOFP: br %r1430;31; CHECK-FP-LABEL: f1:32; CHECK-FP: mvi 4095(%r11), 4233; CHECK-FP: br %r1434 %region1 = alloca [3912 x i8], align 835 %region2 = alloca [3912 x i8], align 836 %ptr1 = getelementptr inbounds [3912 x i8], ptr %region1, i64 0, i64 737 %ptr2 = getelementptr inbounds [3912 x i8], ptr %region2, i64 0, i64 738 store volatile i8 42, ptr %ptr139 store volatile i8 42, ptr %ptr240 ret void41}42 43; Test the first offset that is out-of-range of the 12-bit form.44define void @f2() {45; CHECK-NOFP-LABEL: f2:46; CHECK-NOFP: mviy 4096(%r15), 4247; CHECK-NOFP: br %r1448;49; CHECK-FP-LABEL: f2:50; CHECK-FP: mviy 4096(%r11), 4251; CHECK-FP: br %r1452 %region1 = alloca [3912 x i8], align 853 %region2 = alloca [3912 x i8], align 854 %ptr1 = getelementptr inbounds [3912 x i8], ptr %region1, i64 0, i64 855 %ptr2 = getelementptr inbounds [3912 x i8], ptr %region2, i64 0, i64 856 store volatile i8 42, ptr %ptr157 store volatile i8 42, ptr %ptr258 ret void59}60 61; Test the last offset that is in range of the 20-bit form.62;63; The last in-range doubleword offset is 524280, so by the same reasoning64; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.65define void @f3() {66; CHECK-NOFP-LABEL: f3:67; CHECK-NOFP: mviy 524287(%r15), 4268; CHECK-NOFP: br %r1469;70; CHECK-FP-LABEL: f3:71; CHECK-FP: mviy 524287(%r11), 4272; CHECK-FP: br %r1473 %region1 = alloca [524104 x i8], align 874 %region2 = alloca [524104 x i8], align 875 %ptr1 = getelementptr inbounds [524104 x i8], ptr %region1, i64 0, i64 776 %ptr2 = getelementptr inbounds [524104 x i8], ptr %region2, i64 0, i64 777 store volatile i8 42, ptr %ptr178 store volatile i8 42, ptr %ptr279 ret void80}81 82; Test the first out-of-range offset. We can't use an index register here,83; and the offset is also out of LAY's range, so expect a constant load84; followed by an addition.85define void @f4() {86; CHECK-NOFP-LABEL: f4:87; CHECK-NOFP: llilh %r1, 888; CHECK-NOFP: la %r1, 0(%r1,%r15)89; CHECK-NOFP: mvi 0(%r1), 4290; CHECK-NOFP: br %r1491;92; CHECK-FP-LABEL: f4:93; CHECK-FP: llilh %r1, 894; CHECK-FP: la %r1, 0(%r1,%r11)95; CHECK-FP: mvi 0(%r1), 4296; CHECK-FP: br %r1497 %region1 = alloca [524104 x i8], align 898 %region2 = alloca [524104 x i8], align 899 %ptr1 = getelementptr inbounds [524104 x i8], ptr %region1, i64 0, i64 8100 %ptr2 = getelementptr inbounds [524104 x i8], ptr %region2, i64 0, i64 8101 store volatile i8 42, ptr %ptr1102 store volatile i8 42, ptr %ptr2103 ret void104}105 106; Add 4095 to the previous offset, to test the other end of the MVI range.107; The instruction will actually be STCY before frame lowering.108define void @f5() {109; CHECK-NOFP-LABEL: f5:110; CHECK-NOFP: llilh %r1, 8111; CHECK-NOFP: la %r1, 0(%r1,%r15)112; CHECK-NOFP: mvi 4095(%r1), 42113; CHECK-NOFP: br %r14114;115; CHECK-FP-LABEL: f5:116; CHECK-FP: llilh %r1, 8117; CHECK-FP: la %r1, 0(%r1,%r11)118; CHECK-FP: mvi 4095(%r1), 42119; CHECK-FP: br %r14120 %region1 = alloca [524104 x i8], align 8121 %region2 = alloca [524104 x i8], align 8122 %ptr1 = getelementptr inbounds [524104 x i8], ptr %region1, i64 0, i64 4103123 %ptr2 = getelementptr inbounds [524104 x i8], ptr %region2, i64 0, i64 4103124 store volatile i8 42, ptr %ptr1125 store volatile i8 42, ptr %ptr2126 ret void127}128 129; Test the next offset after that, which uses MVIY instead of MVI.130define void @f6() {131; CHECK-NOFP-LABEL: f6:132; CHECK-NOFP: llilh %r1, 8133; CHECK-NOFP: la %r1, 0(%r1,%r15)134; CHECK-NOFP: mviy 4096(%r1), 42135; CHECK-NOFP: br %r14136;137; CHECK-FP-LABEL: f6:138; CHECK-FP: llilh %r1, 8139; CHECK-FP: la %r1, 0(%r1,%r11)140; CHECK-FP: mviy 4096(%r1), 42141; CHECK-FP: br %r14142 %region1 = alloca [524104 x i8], align 8143 %region2 = alloca [524104 x i8], align 8144 %ptr1 = getelementptr inbounds [524104 x i8], ptr %region1, i64 0, i64 4104145 %ptr2 = getelementptr inbounds [524104 x i8], ptr %region2, i64 0, i64 4104146 store volatile i8 42, ptr %ptr1147 store volatile i8 42, ptr %ptr2148 ret void149}150 151; Now try an offset of 524287 from the start of the object, with the152; object being at offset 1048576 (1 << 20). The backend prefers to create153; anchors 0x10000 bytes apart, so that the high part can be loaded using154; LLILH while still using MVI in more cases than 0x40000 anchors would.155define void @f7() {156; CHECK-NOFP-LABEL: f7:157; CHECK-NOFP: llilh %r1, 23158; CHECK-NOFP: la %r1, 0(%r1,%r15)159; CHECK-NOFP: mviy 65535(%r1), 42160; CHECK-NOFP: br %r14161;162; CHECK-FP-LABEL: f7:163; CHECK-FP: llilh %r1, 23164; CHECK-FP: la %r1, 0(%r1,%r11)165; CHECK-FP: mviy 65535(%r1), 42166; CHECK-FP: br %r14167 %region1 = alloca [1048400 x i8], align 8168 %region2 = alloca [1048400 x i8], align 8169 %ptr1 = getelementptr inbounds [1048400 x i8], ptr %region1, i64 0, i64 524287170 %ptr2 = getelementptr inbounds [1048400 x i8], ptr %region2, i64 0, i64 524287171 store volatile i8 42, ptr %ptr1172 store volatile i8 42, ptr %ptr2173 ret void174}175 176; Keep the object-relative offset the same but bump the size of the177; objects by one doubleword.178define void @f8() {179; CHECK-NOFP-LABEL: f8:180; CHECK-NOFP: llilh %r1, 24181; CHECK-NOFP: la %r1, 0(%r1,%r15)182; CHECK-NOFP: mvi 7(%r1), 42183; CHECK-NOFP: br %r14184;185; CHECK-FP-LABEL: f8:186; CHECK-FP: llilh %r1, 24187; CHECK-FP: la %r1, 0(%r1,%r11)188; CHECK-FP: mvi 7(%r1), 42189; CHECK-FP: br %r14190 %region1 = alloca [1048408 x i8], align 8191 %region2 = alloca [1048408 x i8], align 8192 %ptr1 = getelementptr inbounds [1048408 x i8], ptr %region1, i64 0, i64 524287193 %ptr2 = getelementptr inbounds [1048408 x i8], ptr %region2, i64 0, i64 524287194 store volatile i8 42, ptr %ptr1195 store volatile i8 42, ptr %ptr2196 ret void197}198 199; Check a case where the original displacement is out of range. The backend200; should force separate address logic from the outset. We don't yet do any201; kind of anchor optimization, so there should be no offset on the MVI itself.202;203; Before frame lowering this is an LA followed by the AGFI seen below.204; The LA then gets lowered into the LLILH/LA form. The exact sequence205; isn't that important though.206define void @f9() {207; CHECK-NOFP-LABEL: f9:208; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16209; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)210; CHECK-NOFP: agfi [[R2]], 524288211; CHECK-NOFP: mvi 0([[R2]]), 42212; CHECK-NOFP: br %r14213;214; CHECK-FP-LABEL: f9:215; CHECK-FP: llilh [[R1:%r[1-5]]], 16216; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)217; CHECK-FP: agfi [[R2]], 524288218; CHECK-FP: mvi 0([[R2]]), 42219; CHECK-FP: br %r14220 %region1 = alloca [1048408 x i8], align 8221 %region2 = alloca [1048408 x i8], align 8222 %ptr1 = getelementptr inbounds [1048408 x i8], ptr %region1, i64 0, i64 524288223 %ptr2 = getelementptr inbounds [1048408 x i8], ptr %region2, i64 0, i64 524288224 store volatile i8 42, ptr %ptr1225 store volatile i8 42, ptr %ptr2226 ret void227}228 229; Repeat f4 in a case that needs the emergency spill slots (because all230; call-clobbered registers are live and no call-saved ones have been231; allocated).232define void @f10(ptr %vptr) {233; CHECK-NOFP-LABEL: f10:234; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)235; CHECK-NOFP: llilh [[REGISTER]], 8236; CHECK-NOFP: la [[REGISTER]], 0([[REGISTER]],%r15)237; CHECK-NOFP: mvi 0([[REGISTER]]), 42238; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)239; CHECK-NOFP: br %r14240;241; CHECK-FP-LABEL: f10:242; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)243; CHECK-FP: llilh [[REGISTER]], 8244; CHECK-FP: la [[REGISTER]], 0([[REGISTER]],%r11)245; CHECK-FP: mvi 0([[REGISTER]]), 42246; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)247; CHECK-FP: br %r14248 %i0 = load volatile i32, ptr %vptr249 %i1 = load volatile i32, ptr %vptr250 %i3 = load volatile i32, ptr %vptr251 %i4 = load volatile i32, ptr %vptr252 %i5 = load volatile i32, ptr %vptr253 %region1 = alloca [524104 x i8], align 8254 %region2 = alloca [524104 x i8], align 8255 %ptr1 = getelementptr inbounds [524104 x i8], ptr %region1, i64 0, i64 8256 %ptr2 = getelementptr inbounds [524104 x i8], ptr %region2, i64 0, i64 8257 store volatile i8 42, ptr %ptr1258 store volatile i8 42, ptr %ptr2259 store volatile i32 %i0, ptr %vptr260 store volatile i32 %i1, ptr %vptr261 store volatile i32 %i3, ptr %vptr262 store volatile i32 %i4, ptr %vptr263 store volatile i32 %i5, ptr %vptr264 ret void265}266 267; And again with maximum register pressure. The only spill slots that the268; NOFP case needs are the emergency ones, so the offsets are the same as for f4.269; The FP case needs to spill an extra register and is too dependent on270; register allocation heuristics for a stable test.271define void @f11(ptr %vptr) {272; CHECK-NOFP-LABEL: f11:273; CHECK-NOFP: stmg %r6, %r15,274; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)275; CHECK-NOFP: llilh [[REGISTER]], 8276; CHECK-NOFP: la [[REGISTER]], 0([[REGISTER]],%r15)277; CHECK-NOFP: mvi 0([[REGISTER]]), 42278; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)279; CHECK-NOFP: lmg %r6, %r15,280; CHECK-NOFP: br %r14281 %i0 = load volatile i32, ptr %vptr282 %i1 = load volatile i32, ptr %vptr283 %i3 = load volatile i32, ptr %vptr284 %i4 = load volatile i32, ptr %vptr285 %i5 = load volatile i32, ptr %vptr286 %i6 = load volatile i32, ptr %vptr287 %i7 = load volatile i32, ptr %vptr288 %i8 = load volatile i32, ptr %vptr289 %i9 = load volatile i32, ptr %vptr290 %i10 = load volatile i32, ptr %vptr291 %i11 = load volatile i32, ptr %vptr292 %i12 = load volatile i32, ptr %vptr293 %i13 = load volatile i32, ptr %vptr294 %i14 = load volatile i32, ptr %vptr295 %region1 = alloca [524104 x i8], align 8296 %region2 = alloca [524104 x i8], align 8297 %ptr1 = getelementptr inbounds [524104 x i8], ptr %region1, i64 0, i64 8298 %ptr2 = getelementptr inbounds [524104 x i8], ptr %region2, i64 0, i64 8299 store volatile i8 42, ptr %ptr1300 store volatile i8 42, ptr %ptr2301 store volatile i32 %i0, ptr %vptr302 store volatile i32 %i1, ptr %vptr303 store volatile i32 %i3, ptr %vptr304 store volatile i32 %i4, ptr %vptr305 store volatile i32 %i5, ptr %vptr306 store volatile i32 %i6, ptr %vptr307 store volatile i32 %i7, ptr %vptr308 store volatile i32 %i8, ptr %vptr309 store volatile i32 %i9, ptr %vptr310 store volatile i32 %i10, ptr %vptr311 store volatile i32 %i11, ptr %vptr312 store volatile i32 %i12, ptr %vptr313 store volatile i32 %i13, ptr %vptr314 store volatile i32 %i14, ptr %vptr315 ret void316}317