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1; Test spilling of GPRs. The tests here assume z10 register pressure,2; without the high words being available.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s5 6; We need to allocate a 4-byte spill slot, rounded to 8 bytes. The frame7; size should be exactly 160 + 8 = 168.8define void @f1(ptr %ptr) {9; CHECK-LABEL: f1:10; CHECK: stmg %r6, %r15, 48(%r15)11; CHECK: aghi %r15, -16812; CHECK-NOT: 160(%r15)13; CHECK: st [[REGISTER:%r[0-9]+]], 164(%r15)14; CHECK-NOT: 160(%r15)15; CHECK: l [[REGISTER]], 164(%r15)16; CHECK-NOT: 160(%r15)17; CHECK: lmg %r6, %r15, 216(%r15)18; CHECK: br %r1419 %l0 = load volatile i32, ptr %ptr20 %l1 = load volatile i32, ptr %ptr21 %l3 = load volatile i32, ptr %ptr22 %l4 = load volatile i32, ptr %ptr23 %l5 = load volatile i32, ptr %ptr24 %l6 = load volatile i32, ptr %ptr25 %l7 = load volatile i32, ptr %ptr26 %l8 = load volatile i32, ptr %ptr27 %l9 = load volatile i32, ptr %ptr28 %l10 = load volatile i32, ptr %ptr29 %l11 = load volatile i32, ptr %ptr30 %l12 = load volatile i32, ptr %ptr31 %l13 = load volatile i32, ptr %ptr32 %l14 = load volatile i32, ptr %ptr33 %lx = load volatile i32, ptr %ptr34 store volatile i32 %lx, ptr %ptr35 store volatile i32 %l14, ptr %ptr36 store volatile i32 %l13, ptr %ptr37 store volatile i32 %l12, ptr %ptr38 store volatile i32 %l11, ptr %ptr39 store volatile i32 %l10, ptr %ptr40 store volatile i32 %l9, ptr %ptr41 store volatile i32 %l8, ptr %ptr42 store volatile i32 %l7, ptr %ptr43 store volatile i32 %l6, ptr %ptr44 store volatile i32 %l5, ptr %ptr45 store volatile i32 %l4, ptr %ptr46 store volatile i32 %l3, ptr %ptr47 store volatile i32 %l1, ptr %ptr48 store volatile i32 %l0, ptr %ptr49 ret void50}51 52; Same for i64, except that the full spill slot is used.53define void @f2(ptr %ptr) {54; CHECK-LABEL: f2:55; CHECK: stmg %r6, %r15, 48(%r15)56; CHECK: aghi %r15, -16857; CHECK: stg [[REGISTER:%r[0-9]+]], 160(%r15)58; CHECK: lg [[REGISTER]], 160(%r15)59; CHECK: lmg %r6, %r15, 216(%r15)60; CHECK: br %r1461 %l0 = load volatile i64, ptr %ptr62 %l1 = load volatile i64, ptr %ptr63 %l3 = load volatile i64, ptr %ptr64 %l4 = load volatile i64, ptr %ptr65 %l5 = load volatile i64, ptr %ptr66 %l6 = load volatile i64, ptr %ptr67 %l7 = load volatile i64, ptr %ptr68 %l8 = load volatile i64, ptr %ptr69 %l9 = load volatile i64, ptr %ptr70 %l10 = load volatile i64, ptr %ptr71 %l11 = load volatile i64, ptr %ptr72 %l12 = load volatile i64, ptr %ptr73 %l13 = load volatile i64, ptr %ptr74 %l14 = load volatile i64, ptr %ptr75 %lx = load volatile i64, ptr %ptr76 store volatile i64 %lx, ptr %ptr77 store volatile i64 %l14, ptr %ptr78 store volatile i64 %l13, ptr %ptr79 store volatile i64 %l12, ptr %ptr80 store volatile i64 %l11, ptr %ptr81 store volatile i64 %l10, ptr %ptr82 store volatile i64 %l9, ptr %ptr83 store volatile i64 %l8, ptr %ptr84 store volatile i64 %l7, ptr %ptr85 store volatile i64 %l6, ptr %ptr86 store volatile i64 %l5, ptr %ptr87 store volatile i64 %l4, ptr %ptr88 store volatile i64 %l3, ptr %ptr89 store volatile i64 %l1, ptr %ptr90 store volatile i64 %l0, ptr %ptr91 ret void92}93