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1# RUN: llc -mtriple=s390x-linux-gnu -start-before=prologepilog %s -o - -mcpu=z14 \2# RUN: -debug-only=prologepilog -print-after=prologepilog -verify-machineinstrs 2>&1 \3# RUN: | FileCheck %s4# REQUIRES: asserts5#6# Test that stack objects are ordered in a good way with respect to the7# displacement operands of users.8 9--- |10 define void @f1() { ret void }11 define void @f2() { ret void }12 define void @f3() { ret void }13 define void @f4() { ret void }14 define void @f5() { ret void }15 define void @f6() { ret void }16 17...18 19### Test that %stack.0 is placed close to its D12 user.20# CHECK: alloc FI(1) at SP[-4255]21# CHECK-NEXT: alloc FI(0) at SP[-4271]22# CHECK-NEXT: alloc FI(2) at SP[-4280]23# CHECK-NEXT: alloc FI(3) at SP[-4288]24# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization25# CHECK-NEXT: # Machine code for function f1: IsSSA, NoPHIs, TracksLiveness, NoVRegs26# CHECK-NOT: LAY27# CHECK: VL3228---29name: f130tracksRegLiveness: true31stack:32 - { id: 0, size: 16 }33 - { id: 1, size: 4095 }34machineFunctionInfo: {}35body: |36 bb.0:37 renamable $f0s = VL32 %stack.0, 0, $noreg38 Return39 40...41 42### Test that %stack.1 is placed close to its D12 user.43# CHECK: alloc FI(0) at SP[-176]44# CHECK-NEXT: alloc FI(1) at SP[-4271]45# CHECK-NEXT: alloc FI(2) at SP[-4280]46# CHECK-NEXT: alloc FI(3) at SP[-4288]47# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization48# CHECK-NEXT: # Machine code for function f2: IsSSA, NoPHIs, TracksLiveness, NoVRegs49# CHECK-NOT: LAY50# CHECK: VL3251---52name: f253tracksRegLiveness: true54stack:55 - { id: 0, size: 16 }56 - { id: 1, size: 4095 }57machineFunctionInfo: {}58body: |59 bb.0:60 renamable $f0s = VL32 %stack.1, 3916, $noreg61 Return62 63...64 65### Swap the order of the objects so that both accesses are in range.66# CHECK: alloc FI(1) at SP[-8350]67# CHECK-NEXT: alloc FI(0) at SP[-12445]68# CHECK-NEXT: alloc FI(2) at SP[-12456]69# CHECK-NEXT: alloc FI(3) at SP[-12464]70# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization71# CHECK-NEXT: # Machine code for function f3: IsSSA, NoPHIs, TracksLiveness, NoVRegs72# CHECK-NOT: LAY73# CHECK: VL3274# CHECK-NOT: LAY75# CHECK: LEY76---77name: f378tracksRegLiveness: true79stack:80 - { id: 0, size: 4095 }81 - { id: 1, size: 8190 }82machineFunctionInfo: {}83body: |84 bb.0:85 renamable $f0s = VL32 %stack.0, 0, $noreg86 renamable $f0s = LE %stack.1, 0, $noreg87 Return88 89...90 91### Reorder the objects so that all accesses are in range.92# CHECK: alloc FI(0) at SP[-8350]93# CHECK-NEXT: alloc FI(2) at SP[-16540]94# CHECK-NEXT: alloc FI(3) at SP[-24730]95# CHECK-NEXT: alloc FI(1) at SP[-26777]96# CHECK-NEXT: alloc FI(4) at SP[-28824]97# CHECK-NEXT: alloc FI(5) at SP[-28832]98# CHECK-NEXT: alloc FI(6) at SP[-28840]99# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization100# CHECK-NEXT: # Machine code for function f4: IsSSA, NoPHIs, TracksLiveness, NoVRegs101# CHECK-NOT: LAY102# CHECK: LEY103# CHECK-NEXT: VL32104# CHECK-NEXT: LEY105# CHECK-NEXT: LEY106# CHECK-NEXT: VL32107---108name: f4109tracksRegLiveness: true110stack:111 - { id: 0, size: 8190 }112 - { id: 1, size: 2047 }113 - { id: 2, size: 8190 }114 - { id: 3, size: 8190 }115 - { id: 4, size: 2047 }116machineFunctionInfo: {}117body: |118 bb.0:119 renamable $f2s = LE %stack.0, 0, $noreg120 renamable $f0s = VL32 %stack.1, 0, $noreg121 renamable $f3s = LEY %stack.2, 0, $noreg122 renamable $f4s = LE %stack.3, 0, $noreg123 renamable $f1s = VL32 %stack.4, 0, $noreg124 Return125 126...127 128### Reorder the objects so that the VL32 object is in range and the LYs are129### shortened to Ls (STOC cannot be shortened).130# CHECK: alloc FI(0) at SP[-8350]131# CHECK-NEXT: alloc FI(1) at SP[-16540]132# CHECK-NEXT: alloc FI(2) at SP[-24730]133# CHECK-NEXT: alloc FI(3) at SP[-26777]134# CHECK-NEXT: alloc FI(4) at SP[-26792]135# CHECK-NEXT: alloc FI(5) at SP[-26800]136# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization137# CHECK-NEXT: # Machine code for function f5: IsSSA, NoPHIs, TracksLiveness, NoVRegs138# CHECK-NOT: LAY139# CHECK: $r1l = L $r15140# CHECK-NEXT: $r1l = L $r15141# CHECK-NEXT: IMPLICIT_DEF142# CHECK-NEXT: STOC143# CHECK-NEXT: STOC144# CHECK-NEXT: VL32145---146name: f5147tracksRegLiveness: true148stack:149 - { id: 0, size: 8190 }150 - { id: 1, size: 8190 }151 - { id: 2, size: 8190 }152 - { id: 3, size: 2047 }153machineFunctionInfo: {}154body: |155 bb.0:156 $r1l = LY %stack.2, 0, $noreg157 $r1l = LY %stack.2, 0, $noreg158 $cc = IMPLICIT_DEF159 STOC $r1l, %stack.0, 0, 14, 8, implicit $cc160 STOC $r1l, %stack.1, 0, 14, 8, implicit $cc161 renamable $f3s = VL32 %stack.3, 0, $noreg162 Return163 164...165 166### Test handling of a variable sized object.167# CHECK: alloc FI(1) at SP[-476]168# CHECK-NEXT: alloc FI(0) at SP[-776]169# CHECK-NEXT: alloc FI(2) at SP[-776]170# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization171# CHECK-NEXT: # Machine code for function f6: IsSSA, NoPHIs, TracksLiveness, NoVRegs172 173# CHECK: $r15d = AGHI $r15d(tied-def 0), -776, implicit-def dead $cc174# CHECK: $r11d = LGR $r15d175# CHECK: renamable $r2d = ADJDYNALLOC renamable $r1d, 0, $noreg176# CHECK: VST64 renamable $f0d, $r11d, 160, $noreg177# CHECK: VST32 renamable $f1s, $r11d, 460, $noreg178# CHECK: VST32 killed renamable $f0s, killed renamable $r2d, 0, $noreg179---180name: f6181tracksRegLiveness: true182stack:183 - { id: 0, size: 300 }184 - { id: 1, size: 316 }185 - { id: 2, type: variable-sized }186machineFunctionInfo: {}187body: |188 bb.0 (%ir-block.0):189 liveins: $f0d, $f0s, $f1s, $r2l190 191 renamable $r2l = KILL $r2l, implicit-def $r2d192 renamable $r1d = RISBGN undef renamable $r1d, killed renamable $r2d, 30, 189, 2193 renamable $r0d = nuw LA killed renamable $r1d, 7, $noreg194 renamable $r0d = RISBGN undef renamable $r0d, killed renamable $r0d, 29, 188, 0195 renamable $r1d = SGRK $r15d, killed renamable $r0d, implicit-def dead $cc196 renamable $r2d = ADJDYNALLOC renamable $r1d, 0, $noreg197 $r15d = COPY killed renamable $r1d198 VST64 renamable $f0d, %stack.0, 0, $noreg199 VST32 renamable $f1s, %stack.1, 0, $noreg200 VST32 killed renamable $f0s, killed renamable $r2d, 0, $noreg201 Return202 203...204