776 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -O2 | FileCheck %s3; Test implementation of combining br_ccmask for flag output operand, and4; optimizing ipm sequence using conditional branches.5 6declare void @dummy()7 8; Check a case where the cc is used as an integer.9; Just (srl (ipm)) sequence without optimization.10define i32 @test(ptr %a) {11; CHECK-LABEL: test:12; CHECK: # %bb.0:13; CHECK-NEXT: #APP14; CHECK-NEXT: alsi 0(%r2), -115; CHECK-EMPTY:16; CHECK-NEXT: #NO_APP17; CHECK-NEXT: ipm %r218; CHECK-NEXT: srl %r2, 2819; CHECK-NEXT: br %r1420 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)21 %tmp = icmp ult i32 %cc, 422 tail call void @llvm.assume(i1 %tmp)23 ret i32 %cc24}25 26; Test-1(f1_0_*). Test all 14 valid combinations, where cc is being used for27; branching.28 29; Check (cc == 0).30define void @f1_0_eq_0(ptr %a) {31; CHECK-LABEL: f1_0_eq_0:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: #APP34; CHECK-NEXT: alsi 0(%r2), -135; CHECK-EMPTY:36; CHECK-NEXT: #NO_APP37; CHECK-NEXT: jge dummy@PLT38; CHECK-NEXT: .LBB1_1: # %exit39; CHECK-NEXT: br %r1440entry:41 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)42 %tmp = icmp ult i32 %cc, 443 tail call void @llvm.assume(i1 %tmp)44 %cmp = icmp eq i32 %cc, 045 br i1 %cmp, label %branch, label %exit46branch:47 tail call void @dummy()48 br label %exit49exit:50 ret void51}52 53; Check (cc != 0).54define void @f1_0_ne_0(ptr %a) {55; CHECK-LABEL: f1_0_ne_0:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: #APP58; CHECK-NEXT: alsi 0(%r2), -159; CHECK-EMPTY:60; CHECK-NEXT: #NO_APP61; CHECK-NEXT: jgne dummy@PLT62; CHECK-NEXT: .LBB2_1: # %exit63; CHECK-NEXT: br %r1464entry:65 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)66 %tmp = icmp ult i32 %cc, 467 tail call void @llvm.assume(i1 %tmp)68 %cmp = icmp ugt i32 %cc, 069 br i1 %cmp, label %branch, label %exit70branch:71 tail call void @dummy()72 br label %exit73exit:74 ret void75}76 77; Check (cc == 1).78define void @f1_0_eq_1(ptr %a) {79; CHECK-LABEL: f1_0_eq_1:80; CHECK: # %bb.0: # %entry81; CHECK-NEXT: #APP82; CHECK-NEXT: alsi 0(%r2), -183; CHECK-EMPTY:84; CHECK-NEXT: #NO_APP85; CHECK-NEXT: jgl dummy@PLT86; CHECK-NEXT: .LBB3_1: # %exit87; CHECK-NEXT: br %r1488entry:89 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)90 %tmp = icmp ult i32 %cc, 491 tail call void @llvm.assume(i1 %tmp)92 %cmp = icmp eq i32 %cc, 193 br i1 %cmp, label %branch, label %exit94branch:95 tail call void @dummy()96 br label %exit97exit:98 ret void99}100 101; Check (cc != 1).102define void @f1_0_ne_1(ptr %a) {103; CHECK-LABEL: f1_0_ne_1:104; CHECK: # %bb.0: # %entry105; CHECK-NEXT: #APP106; CHECK-NEXT: alsi 0(%r2), -1107; CHECK-EMPTY:108; CHECK-NEXT: #NO_APP109; CHECK-NEXT: jgnl dummy@PLT110; CHECK-NEXT: .LBB4_1: # %exit111; CHECK-NEXT: br %r14112entry:113 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)114 %tmp = icmp ult i32 %cc, 4115 tail call void @llvm.assume(i1 %tmp)116 %cmp = icmp ne i32 %cc, 1117 br i1 %cmp, label %branch, label %exit118branch:119 tail call void @dummy()120 br label %exit121exit:122 ret void123}124 125; Check (cc == 2).126define void @f1_0_eq_2(ptr %a) {127; CHECK-LABEL: f1_0_eq_2:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: #APP130; CHECK-NEXT: alsi 0(%r2), -1131; CHECK-EMPTY:132; CHECK-NEXT: #NO_APP133; CHECK-NEXT: jgh dummy@PLT134; CHECK-NEXT: .LBB5_1: # %exit135; CHECK-NEXT: br %r14136entry:137 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)138 %tmp = icmp ult i32 %cc, 4139 tail call void @llvm.assume(i1 %tmp)140 %cmp = icmp eq i32 %cc, 2141 br i1 %cmp, label %branch, label %exit142branch:143 tail call void @dummy()144 br label %exit145exit:146 ret void147}148 149; Check (cc != 2).150define void @f1_0_ne_2(ptr %a) {151; CHECK-LABEL: f1_0_ne_2:152; CHECK: # %bb.0: # %entry153; CHECK-NEXT: #APP154; CHECK-NEXT: alsi 0(%r2), -1155; CHECK-EMPTY:156; CHECK-NEXT: #NO_APP157; CHECK-NEXT: jgnh dummy@PLT158; CHECK-NEXT: .LBB6_1: # %exit159; CHECK-NEXT: br %r14160entry:161 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)162 %tmp = icmp ult i32 %cc, 4163 tail call void @llvm.assume(i1 %tmp)164 %cmp = icmp ne i32 %cc, 2165 br i1 %cmp, label %branch, label %exit166branch:167 tail call void @dummy()168 br label %exit169exit:170 ret void171}172 173; Check (cc == 3).174define void @f1_0_eq_3(ptr %a) {175; CHECK-LABEL: f1_0_eq_3:176; CHECK: # %bb.0: # %entry177; CHECK-NEXT: #APP178; CHECK-NEXT: alsi 0(%r2), -1179; CHECK-EMPTY:180; CHECK-NEXT: #NO_APP181; CHECK-NEXT: jgo dummy@PLT182; CHECK-NEXT: .LBB7_1: # %exit183; CHECK-NEXT: br %r14184entry:185 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)186 %tmp = icmp ult i32 %cc, 4187 tail call void @llvm.assume(i1 %tmp)188 %cmp = icmp eq i32 %cc, 3189 br i1 %cmp, label %branch, label %exit190branch:191 tail call void @dummy()192 br label %exit193exit:194 ret void195}196 197; Check (cc != 3).198define void @f1_0_ne_3(ptr %a) {199; CHECK-LABEL: f1_0_ne_3:200; CHECK: # %bb.0: # %entry201; CHECK-NEXT: #APP202; CHECK-NEXT: alsi 0(%r2), -1203; CHECK-EMPTY:204; CHECK-NEXT: #NO_APP205; CHECK-NEXT: jgno dummy@PLT206; CHECK-NEXT: .LBB8_1: # %exit207; CHECK-NEXT: br %r14208entry:209 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)210 %tmp = icmp ult i32 %cc, 4211 tail call void @llvm.assume(i1 %tmp)212 %cmp = icmp ult i32 %cc, 3213 br i1 %cmp, label %branch, label %exit214branch:215 tail call void @dummy()216 br label %exit217exit:218 ret void219}220 221; Check (cc == 0|1).222define void @f1_0_01(ptr %a) {223; CHECK-LABEL: f1_0_01:224; CHECK: # %bb.0: # %entry225; CHECK-NEXT: #APP226; CHECK-NEXT: alsi 0(%r2), -1227; CHECK-EMPTY:228; CHECK-NEXT: #NO_APP229; CHECK-NEXT: jgle dummy@PLT230; CHECK-NEXT: .LBB9_1: # %exit231; CHECK-NEXT: br %r14232entry:233 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)234 %tmp = icmp ult i32 %cc, 4235 tail call void @llvm.assume(i1 %tmp)236 %cmp = icmp ult i32 %cc, 2237 br i1 %cmp, label %branch, label %exit238branch:239 tail call void @dummy()240 br label %exit241exit:242 ret void243}244 245; Check (cc == 0|2).246define void @f1_0_02(ptr %a) {247; CHECK-LABEL: f1_0_02:248; CHECK: # %bb.0: # %entry249; CHECK-NEXT: #APP250; CHECK-NEXT: alsi 0(%r2), -1251; CHECK-EMPTY:252; CHECK-NEXT: #NO_APP253; CHECK-NEXT: jghe dummy@PLT254; CHECK-NEXT: .LBB10_1: # %exit255; CHECK-NEXT: br %r14256entry:257 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)258 %tmp = icmp ult i32 %cc, 4259 tail call void @llvm.assume(i1 %tmp)260 %and = and i32 %cc, 1261 %cmp = icmp eq i32 %and, 0262 br i1 %cmp, label %branch, label %exit263branch:264 tail call void @dummy()265 br label %exit266exit:267 ret void268}269 270; Check (cc == 0|3).271define void @f1_0_03(ptr %a) {272; CHECK-LABEL: f1_0_03:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: #APP275; CHECK-NEXT: alsi 0(%r2), -1276; CHECK-EMPTY:277; CHECK-NEXT: #NO_APP278; CHECK-NEXT: jgnlh dummy@PLT279; CHECK-NEXT: .LBB11_1: # %exit280; CHECK-NEXT: br %r14281entry:282 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)283 %tmp = icmp ult i32 %cc, 4284 tail call void @llvm.assume(i1 %tmp)285 %cmp0 = icmp ne i32 %cc, 0286 %cmp3 = icmp ne i32 %cc, 3287 %cmp.inv = and i1 %cmp0, %cmp3288 br i1 %cmp.inv, label %exit, label %branch289branch:290 tail call void @dummy()291 br label %exit292exit:293 ret void294}295 296; Check (cc == 1|2).297define void @f1_0_12(ptr %a) {298; CHECK-LABEL: f1_0_12:299; CHECK: # %bb.0: # %entry300; CHECK-NEXT: #APP301; CHECK-NEXT: alsi 0(%r2), -1302; CHECK-EMPTY:303; CHECK-NEXT: #NO_APP304; CHECK-NEXT: jglh dummy@PLT305; CHECK-NEXT: .LBB12_1: # %exit306; CHECK-NEXT: br %r14307entry:308 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)309 %tmp = icmp ult i32 %cc, 4310 tail call void @llvm.assume(i1 %tmp)311 %cmpeq1 = icmp eq i32 %cc, 1312 %cmpeq2 = icmp eq i32 %cc, 2313 %cmp = or i1 %cmpeq1, %cmpeq2314 br i1 %cmp, label %branch, label %exit315branch:316 tail call void @dummy()317 br label %exit318exit:319 ret void320}321 322; Check (cc == 1|3).323define void @f1_0_13(ptr %a) {324; CHECK-LABEL: f1_0_13:325; CHECK: # %bb.0: # %entry326; CHECK-NEXT: #APP327; CHECK-NEXT: alsi 0(%r2), -1328; CHECK-EMPTY:329; CHECK-NEXT: #NO_APP330; CHECK-NEXT: jgnhe dummy@PLT331; CHECK-NEXT: .LBB13_1: # %exit332; CHECK-NEXT: br %r14333entry:334 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)335 %tmp = icmp ult i32 %cc, 4336 tail call void @llvm.assume(i1 %tmp)337 %cmpeq1 = icmp eq i32 %cc, 1338 %cmpeq3 = icmp eq i32 %cc, 3339 %cmp = or i1 %cmpeq1, %cmpeq3340 br i1 %cmp, label %branch, label %exit341branch:342 tail call void @dummy()343 br label %exit344exit:345 ret void346}347 348; Check (cc == 2|3).349define void @f1_0_23(ptr %a) {350; CHECK-LABEL: f1_0_23:351; CHECK: # %bb.0: # %entry352; CHECK-NEXT: #APP353; CHECK-NEXT: alsi 0(%r2), -1354; CHECK-EMPTY:355; CHECK-NEXT: #NO_APP356; CHECK-NEXT: jgnle dummy@PLT357; CHECK-NEXT: .LBB14_1: # %exit358; CHECK-NEXT: br %r14359entry:360 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)361 %tmp = icmp ult i32 %cc, 4362 tail call void @llvm.assume(i1 %tmp)363 %cmp = icmp ugt i32 %cc, 1364 br i1 %cmp, label %branch, label %exit365branch:366 tail call void @dummy()367 br label %exit368exit:369 ret void370}371 372; Test-2(f1_1_*/f1_2_*/fl_3_*/f1_4_*).373; Test Mixed patterns involving Binary Ops.374 375; Check 'add' for (cc != 0).376define void @f1_1_1(ptr %a) {377; CHECK-LABEL: f1_1_1:378; CHECK: # %bb.0: # %entry379; CHECK-NEXT: #APP380; CHECK-NEXT: alsi 0(%r2), -1381; CHECK-EMPTY:382; CHECK-NEXT: #NO_APP383; CHECK-NEXT: jgne dummy@PLT384; CHECK-NEXT: .LBB15_1: # %exit385; CHECK-NEXT: br %r14386entry:387 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)388 %tmp = icmp ult i32 %cc, 4389 tail call void @llvm.assume(i1 %tmp)390 %add = add nsw i32 %cc, -1391 %cmp = icmp ult i32 %add, 3392 br i1 %cmp, label %branch, label %exit393branch:394 tail call void @dummy()395 br label %exit396exit:397 ret void398}399 400; Check 'add' for (cc == 1|2).401define void @f1_1_2(ptr %a) {402; CHECK-LABEL: f1_1_2:403; CHECK: # %bb.0: # %entry404; CHECK-NEXT: #APP405; CHECK-NEXT: alsi 0(%r2), -1406; CHECK-EMPTY:407; CHECK-NEXT: #NO_APP408; CHECK-NEXT: jglh dummy@PLT409; CHECK-NEXT: .LBB16_1: # %exit410; CHECK-NEXT: br %r14411entry:412 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)413 %tmp = icmp ult i32 %cc, 4414 tail call void @llvm.assume(i1 %tmp)415 %add = add nsw i32 %cc, -1416 %cmp = icmp ult i32 %add, 2417 br i1 %cmp, label %branch, label %exit418branch:419 tail call void @dummy()420 br label %exit421exit:422 ret void423}424 425; Check 'add' for (cc == 1|2).426define void @f1_1_3(ptr %a) {427; CHECK-LABEL: f1_1_3:428; CHECK: # %bb.0: # %entry429; CHECK-NEXT: #APP430; CHECK-NEXT: alsi 0(%r2), -1431; CHECK-EMPTY:432; CHECK-NEXT: #NO_APP433; CHECK-NEXT: jglh dummy@PLT434; CHECK-NEXT: .LBB17_1: # %exit435; CHECK-NEXT: br %r14436entry:437 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)438 %tmp = icmp ult i32 %cc, 4439 tail call void @llvm.assume(i1 %tmp)440 %add = add nsw i32 %cc, -3441 %cmp.inv = icmp ult i32 %add, -2442 br i1 %cmp.inv, label %exit, label %branch443branch:444 tail call void @dummy()445 br label %exit446exit:447 ret void448}449 450; Check 'and' with one operand cc and other select_ccmask(cc !=1).451define void @f1_2_1(ptr %a) {452; CHECK-LABEL: f1_2_1:453; CHECK: # %bb.0: # %entry454; CHECK-NEXT: #APP455; CHECK-NEXT: alsi 0(%r2), -1456; CHECK-EMPTY:457; CHECK-NEXT: #NO_APP458; CHECK-NEXT: jgnl dummy@PLT459; CHECK-NEXT: .LBB18_1: # %exit460; CHECK-NEXT: br %r14461entry:462 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)463 %tmp = icmp ult i32 %cc, 4464 tail call void @llvm.assume(i1 %tmp)465 %andcc = and i32 %cc, 1466 %cmpne0 = icmp ne i32 %andcc, 0467 %cmpne3 = icmp ne i32 %cc, 3468 %cmp.inv = and i1 %cmpne3, %cmpne0469 br i1 %cmp.inv, label %exit, label %branch470branch:471 tail call void @dummy()472 br label %exit473exit:474 ret void475}476 477; Check 'and' with both operands select_ccmask(cc != 2).478define void @f1_2_2(ptr %a) {479; CHECK-LABEL: f1_2_2:480; CHECK: # %bb.0: # %entry481; CHECK-NEXT: #APP482; CHECK-NEXT: alsi 0(%r2), -1483; CHECK-EMPTY:484; CHECK-NEXT: #NO_APP485; CHECK-NEXT: jgnh dummy@PLT486; CHECK-NEXT: .LBB19_1: # %exit487; CHECK-NEXT: br %r14488entry:489 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)490 %tmp = icmp ult i32 %cc, 4491 tail call void @llvm.assume(i1 %tmp)492 %ugt1 = icmp samesign ugt i32 %cc, 1493 %cmpne3 = icmp ne i32 %cc, 3494 %and.cond.inv = and i1 %ugt1, %cmpne3495 br i1 %and.cond.inv, label %exit, label %branch496branch:497 tail call void @dummy()498 br label %exit499exit:500 ret void501}502 503; Check 'and/tm' for (cc == 0|2).504define void @f1_2_3(ptr %a) {505; CHECK-LABEL: f1_2_3:506; CHECK: # %bb.0: # %entry507; CHECK-NEXT: #APP508; CHECK-NEXT: alsi 0(%r2), -1509; CHECK-EMPTY:510; CHECK-NEXT: #NO_APP511; CHECK-NEXT: jghe dummy@PLT512; CHECK-NEXT: .LBB20_1: # %exit513; CHECK-NEXT: br %r14514entry:515 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)516 %tmp = icmp ult i32 %cc, 4517 tail call void @llvm.assume(i1 %tmp)518 %and = and i32 %cc, 1519 %cmp = icmp eq i32 %and, 0520 br i1 %cmp, label %branch, label %exit521branch:522 tail call void @dummy()523 br label %exit524exit:525 ret void526}527 528; Check 'and/tm' for (cc == 1|3).529define void @f1_2_4(ptr %a) {530; CHECK-LABEL: f1_2_4:531; CHECK: # %bb.0: # %entry532; CHECK-NEXT: #APP533; CHECK-NEXT: alsi 0(%r2), -1534; CHECK-EMPTY:535; CHECK-NEXT: #NO_APP536; CHECK-NEXT: jgnhe dummy@PLT537; CHECK-NEXT: .LBB21_1: # %exit538; CHECK-NEXT: br %r14539entry:540 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)541 %tmp = icmp ult i32 %cc, 4542 tail call void @llvm.assume(i1 %tmp)543 %and = and i32 %cc, 1544 %cmp = icmp eq i32 %and, 0545 br i1 %cmp, label %exit, label %branch546branch:547 tail call void @dummy()548 br label %exit549exit:550 ret void551}552 553; Check 'icmp' with one operand 'and' and other 'select_ccmask'(cc != 1).554define void @f1_2_5(ptr %a) {555; CHECK-LABEL: f1_2_5:556; CHECK: # %bb.0: # %entry557; CHECK-NEXT: #APP558; CHECK-NEXT: alsi 0(%r2), -1559; CHECK-EMPTY:560; CHECK-NEXT: #NO_APP561; CHECK-NEXT: jgnl dummy@PLT562; CHECK-NEXT: .LBB22_1: # %exit563; CHECK-NEXT: br %r14564entry:565 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)566 %tmp = icmp ult i32 %cc, 4567 tail call void @llvm.assume(i1 %tmp)568 %trunc = trunc i32 %cc to i1569 %cmpne3 = icmp ne i32 %cc, 3570 %cmp = xor i1 %cmpne3, %trunc571 br i1 %cmp, label %branch, label %exit572branch:573 tail call void @dummy()574 br label %exit575exit:576 ret void577}578 579; Check nested 'xor' cc with select_ccmask(cc != 1).580define void @f1_3_1(ptr %a) {581; CHECK-LABEL: f1_3_1:582; CHECK: # %bb.0: # %entry583; CHECK-NEXT: #APP584; CHECK-NEXT: alsi 0(%r2), -1585; CHECK-EMPTY:586; CHECK-NEXT: #NO_APP587; CHECK-NEXT: jgnl dummy@PLT588; CHECK-NEXT: .LBB23_1: # %exit589; CHECK-NEXT: br %r14590entry:591 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)592 %tmp = icmp ult i32 %cc, 4593 tail call void @llvm.assume(i1 %tmp)594 %cmpeq0 = icmp eq i32 %cc, 0595 %cmpeq2 = icmp eq i32 %cc, 2596 %xor = xor i1 %cmpeq0, %cmpeq2597 %cmpne3 = icmp ne i32 %cc, 3598 %cmp.inv = xor i1 %cmpne3, %xor599 br i1 %cmp.inv, label %exit, label %branch600branch:601 tail call void @dummy()602 br label %exit603exit:604 ret void605}606 607; Check branching on 'tm' and 'xor' with one operand cc and the other608; select_ccmask(cc !=1).609define void @f1_3_2(ptr %a) {610; CHECK-LABEL: f1_3_2:611; CHECK: # %bb.0: # %entry612; CHECK-NEXT: #APP613; CHECK-NEXT: alsi 0(%r2), -1614; CHECK-EMPTY:615; CHECK-NEXT: #NO_APP616; CHECK-NEXT: jgnl dummy@PLT617; CHECK-NEXT: .LBB24_1: # %exit618; CHECK-NEXT: br %r14619entry:620 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)621 %tmp = icmp ult i32 %cc, 4622 tail call void @llvm.assume(i1 %tmp)623 %trunc = trunc i32 %cc to i1624 %cmpeq3 = icmp eq i32 %cc, 3625 %cmp.inv = xor i1 %cmpeq3, %trunc626 br i1 %cmp.inv, label %exit, label %branch627branch:628 tail call void @dummy()629 br label %exit630exit:631 ret void632}633 634; Check branching on 'tm' and 'xor' with one operand cc and the other635; select_ccmask(cc !=2).636define void @f1_3_3(ptr %a) {637; CHECK-LABEL: f1_3_3:638; CHECK: # %bb.0: # %entry639; CHECK-NEXT: #APP640; CHECK-NEXT: alsi 0(%r2), -1641; CHECK-EMPTY:642; CHECK-NEXT: #NO_APP643; CHECK-NEXT: jgnh dummy@PLT644; CHECK-NEXT: .LBB25_1: # %exit645; CHECK-NEXT: br %r14646entry:647 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)648 %tmp = icmp ult i32 %cc, 4649 tail call void @llvm.assume(i1 %tmp)650 %trunc = trunc i32 %cc to i1651 %cmpne0 = icmp ne i32 %cc, 0652 %cmp.cond.inv = xor i1 %cmpne0, %trunc653 br i1 %cmp.cond.inv, label %exit, label %branch654branch:655 tail call void @dummy()656 br label %exit657exit:658 ret void659}660 661; Check 'or' with both operands are select_ccmask one with TM and other with662; ICMP(cc == 1).663define void @f1_4_1(ptr %a) {664; CHECK-LABEL: f1_4_1:665; CHECK: # %bb.0: # %entry666; CHECK-NEXT: #APP667; CHECK-NEXT: alsi 0(%r2), -1668; CHECK-EMPTY:669; CHECK-NEXT: #NO_APP670; CHECK-NEXT: jgl dummy@PLT671; CHECK-NEXT: .LBB26_1: # %exit672; CHECK-NEXT: br %r14673entry:674 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)675 %tmp = icmp ult i32 %cc, 4676 tail call void @llvm.assume(i1 %tmp)677 %andcc = and i32 %cc, 1678 %cmpeq0 = icmp eq i32 %andcc, 0679 %cmpeq3 = icmp eq i32 %cc, 3680 %cmp.cond.inv = or i1 %cmpeq3, %cmpeq0681 br i1 %cmp.cond.inv, label %exit, label %branch682branch:683 tail call void @dummy()684 br label %exit685exit:686 ret void687}688 689; Check 'or' for (cc == 0|1).690define void @f1_4_2(ptr %a) {691; CHECK-LABEL: f1_4_2:692; CHECK: # %bb.0: # %entry693; CHECK-NEXT: #APP694; CHECK-NEXT: alsi 0(%r2), -1695; CHECK-EMPTY:696; CHECK-NEXT: #NO_APP697; CHECK-NEXT: jgle dummy@PLT698; CHECK-NEXT: .LBB27_1: # %exit699; CHECK-NEXT: br %r14700entry:701 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)702 %tmp = icmp ult i32 %cc, 4703 tail call void @llvm.assume(i1 %tmp)704 %or = or disjoint i32 %cc, -4705 %cmp.inv = icmp samesign ugt i32 %or, -3706 br i1 %cmp.inv, label %exit, label %branch707branch:708 tail call void @dummy()709 br label %exit710exit:711 ret void712}713 714; Check 'or' for (cc == 0|1).715define void @f1_4_3(ptr %a) {716; CHECK-LABEL: f1_4_3:717; CHECK: # %bb.0: # %entry718; CHECK-NEXT: #APP719; CHECK-NEXT: alsi 0(%r2), -1720; CHECK-EMPTY:721; CHECK-NEXT: #NO_APP722; CHECK-NEXT: jgle dummy@PLT723; CHECK-NEXT: .LBB28_1: # %exit724; CHECK-NEXT: br %r14725entry:726 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)727 %tmp = icmp ult i32 %cc, 4728 tail call void @llvm.assume(i1 %tmp)729 %or = or disjoint i32 %cc, -4730 %cmp = icmp samesign ult i32 %or, -2731 br i1 %cmp, label %branch, label %exit732branch:733 tail call void @dummy()734 br label %exit735exit:736 ret void737}738 739; Test INLINEASM defines CC.740@wait_fence = global i32 0, align 4741@bit_cc = global i32 0, align 4742define void @test_inlineasm_define_cc() {743; CHECK-LABEL: test_inlineasm_define_cc:744; CHECK: # %bb.0: # %entry745; CHECK-NEXT: lgrl %r1, wait_fence@GOT746; CHECK-NEXT: chsi 0(%r1), 0747; CHECK-NEXT: ber %r14748; CHECK-NEXT: .LBB29_1: # %while.body.lr.ph749; CHECK-NEXT: lgrl %r1, bit_cc@GOT750; CHECK-NEXT: #APP751; CHECK-NEXT: #NO_APP752; CHECK-NEXT: ipm %r0753; CHECK-NEXT: srl %r0, 28754; CHECK-NEXT: st %r0, 0(%r1)755; CHECK-NEXT: .LBB29_2: # %while.body756; CHECK-NEXT: # =>This Inner Loop Header: Depth=1757; CHECK-NEXT: j .LBB29_2758entry:759 %0 = load i32, ptr @wait_fence, align 4760 %tobool.not = icmp eq i32 %0, 0761 br i1 %tobool.not, label %while.end, label %while.body.lr.ph762 763while.body.lr.ph:764 %1 = tail call i32 asm "", "={@cc}"()765 %2 = icmp ult i32 %1, 4766 tail call void @llvm.assume(i1 %2)767 store i32 %1, ptr @bit_cc, align 4768 br label %while.body769 770while.body:771 br label %while.body772 773while.end:774 ret void775}776