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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -O2 | FileCheck %s3; Test implementation of combining select_ccmask for flag output operand and4; optimizing ipm sequence using conditional branches.5 6; Test-1(f2_0_*): Both TrueVal and FalseVal non-const(14-valid CCMask).7 8; Check (cc == 0).9define i64 @f2_0_eq_0(i64 %x, i64 %y, ptr %a) {10; CHECK-LABEL: f2_0_eq_0:11; CHECK: # %bb.0: # %entry12; CHECK-NEXT: #APP13; CHECK-NEXT: alsi 0(%r4), -114; CHECK-EMPTY:15; CHECK-NEXT: #NO_APP16; CHECK-NEXT: ber %r1417; CHECK-NEXT: .LBB0_1: # %entry18; CHECK-NEXT: lgr %r2, %r319; CHECK-NEXT: br %r1420entry:21 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)22 %cmp = icmp ult i32 %cc, 423 tail call void @llvm.assume(i1 %cmp)24 %cond = icmp eq i32 %cc, 025 %res = select i1 %cond, i64 %x, i64 %y26 ret i64 %res27}28 29; Check (cc != 0).30define i64 @f2_0_ne_0(i64 %x, i64 %y, ptr %a) {31; CHECK-LABEL: f2_0_ne_0:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: #APP34; CHECK-NEXT: alsi 0(%r4), -135; CHECK-EMPTY:36; CHECK-NEXT: #NO_APP37; CHECK-NEXT: bner %r1438; CHECK-NEXT: .LBB1_1: # %entry39; CHECK-NEXT: lgr %r2, %r340; CHECK-NEXT: br %r1441entry:42 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)43 %cmp = icmp ult i32 %cc, 444 tail call void @llvm.assume(i1 %cmp)45 %cond = icmp ugt i32 %cc, 046 %res = select i1 %cond, i64 %x, i64 %y47 ret i64 %res48}49 50; Check (cc == 1).51define i64 @f2_0_eq_1(i64 %x, i64 %y, ptr %a) {52; CHECK-LABEL: f2_0_eq_1:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: #APP55; CHECK-NEXT: alsi 0(%r4), -156; CHECK-EMPTY:57; CHECK-NEXT: #NO_APP58; CHECK-NEXT: blr %r1459; CHECK-NEXT: .LBB2_1: # %entry60; CHECK-NEXT: lgr %r2, %r361; CHECK-NEXT: br %r1462entry:63 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)64 %cmp = icmp ult i32 %cc, 465 tail call void @llvm.assume(i1 %cmp)66 %cond = icmp eq i32 %cc, 167 %res = select i1 %cond, i64 %x, i64 %y68 ret i64 %res69}70 71; Check (cc != 1).72define i64 @f2_0_ne_1(i64 %x, i64 %y, ptr %a) {73; CHECK-LABEL: f2_0_ne_1:74; CHECK: # %bb.0: # %entry75; CHECK-NEXT: #APP76; CHECK-NEXT: alsi 0(%r4), -177; CHECK-EMPTY:78; CHECK-NEXT: #NO_APP79; CHECK-NEXT: bnlr %r1480; CHECK-NEXT: .LBB3_1: # %entry81; CHECK-NEXT: lgr %r2, %r382; CHECK-NEXT: br %r1483entry:84 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)85 %cmp = icmp ult i32 %cc, 486 tail call void @llvm.assume(i1 %cmp)87 %cond = icmp ne i32 %cc, 188 %res = select i1 %cond, i64 %x, i64 %y89 ret i64 %res90}91 92; Check (cc == 2).93define i64 @f2_0_eq_2(i64 %x, i64 %y, ptr %a) {94; CHECK-LABEL: f2_0_eq_2:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: #APP97; CHECK-NEXT: alsi 0(%r4), -198; CHECK-EMPTY:99; CHECK-NEXT: #NO_APP100; CHECK-NEXT: bhr %r14101; CHECK-NEXT: .LBB4_1: # %entry102; CHECK-NEXT: lgr %r2, %r3103; CHECK-NEXT: br %r14104entry:105 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)106 %cmp = icmp ult i32 %cc, 4107 tail call void @llvm.assume(i1 %cmp)108 %cond = icmp eq i32 %cc, 2109 %res = select i1 %cond, i64 %x, i64 %y110 ret i64 %res111}112 113; Check (cc != 2).114define i64 @f2_0_ne_2(i64 %x, i64 %y, ptr %a) {115; CHECK-LABEL: f2_0_ne_2:116; CHECK: # %bb.0: # %entry117; CHECK-NEXT: #APP118; CHECK-NEXT: alsi 0(%r4), -1119; CHECK-EMPTY:120; CHECK-NEXT: #NO_APP121; CHECK-NEXT: bnhr %r14122; CHECK-NEXT: .LBB5_1: # %entry123; CHECK-NEXT: lgr %r2, %r3124; CHECK-NEXT: br %r14125entry:126 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)127 %cmp = icmp ult i32 %cc, 4128 tail call void @llvm.assume(i1 %cmp)129 %cond = icmp ne i32 %cc, 2130 %res = select i1 %cond, i64 %x, i64 %y131 ret i64 %res132}133 134; Check (cc == 3).135define i64 @f2_0_eq_3(i64 %x, i64 %y, ptr %a) {136; CHECK-LABEL: f2_0_eq_3:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: #APP139; CHECK-NEXT: alsi 0(%r4), -1140; CHECK-EMPTY:141; CHECK-NEXT: #NO_APP142; CHECK-NEXT: bor %r14143; CHECK-NEXT: .LBB6_1: # %entry144; CHECK-NEXT: lgr %r2, %r3145; CHECK-NEXT: br %r14146entry:147 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)148 %cmp = icmp ult i32 %cc, 4149 tail call void @llvm.assume(i1 %cmp)150 %cond = icmp eq i32 %cc, 3151 %res = select i1 %cond, i64 %x, i64 %y152 ret i64 %res153}154 155; Check (cc != 3).156define i64 @f2_0_ne_3(i64 %x, i64 %y, ptr %a) {157; CHECK-LABEL: f2_0_ne_3:158; CHECK: # %bb.0: # %entry159; CHECK-NEXT: #APP160; CHECK-NEXT: alsi 0(%r4), -1161; CHECK-EMPTY:162; CHECK-NEXT: #NO_APP163; CHECK-NEXT: bnor %r14164; CHECK-NEXT: .LBB7_1: # %entry165; CHECK-NEXT: lgr %r2, %r3166; CHECK-NEXT: br %r14167entry:168 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)169 %cmp = icmp ult i32 %cc, 4170 tail call void @llvm.assume(i1 %cmp)171 %cond = icmp ult i32 %cc, 3172 %res = select i1 %cond, i64 %x, i64 %y173 ret i64 %res174}175 176; Check (cc == 0|1).177define i64 @f2_0_01(i64 %x, i64 %y, ptr %a) {178; CHECK-LABEL: f2_0_01:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: #APP181; CHECK-NEXT: alsi 0(%r4), -1182; CHECK-EMPTY:183; CHECK-NEXT: #NO_APP184; CHECK-NEXT: bler %r14185; CHECK-NEXT: .LBB8_1: # %entry186; CHECK-NEXT: lgr %r2, %r3187; CHECK-NEXT: br %r14188entry:189 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)190 %cmp = icmp ult i32 %cc, 4191 tail call void @llvm.assume(i1 %cmp)192 %cond = icmp ult i32 %cc, 2193 %res = select i1 %cond, i64 %x, i64 %y194 ret i64 %res195}196 197; Check (cc == 0|2).198define i64 @f2_0_02(i64 %x, i64 %y, ptr %a) {199; CHECK-LABEL: f2_0_02:200; CHECK: # %bb.0: # %entry201; CHECK-NEXT: #APP202; CHECK-NEXT: alsi 0(%r4), -1203; CHECK-EMPTY:204; CHECK-NEXT: #NO_APP205; CHECK-NEXT: bher %r14206; CHECK-NEXT: .LBB9_1: # %entry207; CHECK-NEXT: lgr %r2, %r3208; CHECK-NEXT: br %r14209entry:210 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)211 %cmp = icmp ult i32 %cc, 4212 tail call void @llvm.assume(i1 %cmp)213 %and = and i32 %cc, 1214 %cond = icmp eq i32 %and, 0215 %res = select i1 %cond, i64 %x, i64 %y216 ret i64 %res217}218 219; Check (cc == 0|3).220define i64 @f2_0_03(i64 %y, i64 %x, ptr %a) {221; CHECK-LABEL: f2_0_03:222; CHECK: # %bb.0: # %entry223; CHECK-NEXT: #APP224; CHECK-NEXT: alsi 0(%r4), -1225; CHECK-EMPTY:226; CHECK-NEXT: #NO_APP227; CHECK-NEXT: blhr %r14228; CHECK-NEXT: .LBB10_1: # %entry229; CHECK-NEXT: lgr %r2, %r3230; CHECK-NEXT: br %r14231entry:232 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)233 %cmp = icmp ult i32 %cc, 4234 tail call void @llvm.assume(i1 %cmp)235 %cmp0 = icmp ne i32 %cc, 0236 %cmp3 = icmp ne i32 %cc, 3237 %cond.inv = and i1 %cmp0, %cmp3238 %res = select i1 %cond.inv, i64 %y, i64 %x239 ret i64 %res240}241 242; Check (cc == 1|2).243define i64 @f2_0_12(i64 %y, i64 %x, ptr %a) {244; CHECK-LABEL: f2_0_12:245; CHECK: # %bb.0: # %entry246; CHECK-NEXT: #APP247; CHECK-NEXT: alsi 0(%r4), -1248; CHECK-EMPTY:249; CHECK-NEXT: #NO_APP250; CHECK-NEXT: bnlhr %r14251; CHECK-NEXT: .LBB11_1: # %entry252; CHECK-NEXT: lgr %r2, %r3253; CHECK-NEXT: br %r14254entry:255 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)256 %cmp = icmp ult i32 %cc, 4257 tail call void @llvm.assume(i1 %cmp)258 %add = add nsw i32 %cc, -3259 %cond.inv = icmp ult i32 %add, -2260 %res = select i1 %cond.inv, i64 %y, i64 %x261 ret i64 %res262}263 264; Check (cc == 1|3).265define i64 @f2_0_13(i64 %y, i64 %x, ptr %a) {266; CHECK-LABEL: f2_0_13:267; CHECK: # %bb.0: # %entry268; CHECK-NEXT: #APP269; CHECK-NEXT: alsi 0(%r4), -1270; CHECK-EMPTY:271; CHECK-NEXT: #NO_APP272; CHECK-NEXT: bher %r14273; CHECK-NEXT: .LBB12_1: # %entry274; CHECK-NEXT: lgr %r2, %r3275; CHECK-NEXT: br %r14276entry:277 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)278 %cmp = icmp ult i32 %cc, 4279 tail call void @llvm.assume(i1 %cmp)280 %and = and i32 %cc, 1281 %cond.inv = icmp eq i32 %and, 0282 %res = select i1 %cond.inv, i64 %y, i64 %x283 ret i64 %res284}285 286; Check (cc == 2|3).287define i64 @f2_0_23(i64 %x, i64 %y, ptr %a) {288; CHECK-LABEL: f2_0_23:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: #APP291; CHECK-NEXT: alsi 0(%r4), -1292; CHECK-EMPTY:293; CHECK-NEXT: #NO_APP294; CHECK-NEXT: bnler %r14295; CHECK-NEXT: .LBB13_1: # %entry296; CHECK-NEXT: lgr %r2, %r3297; CHECK-NEXT: br %r14298entry:299 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)300 %cmp = icmp ult i32 %cc, 4301 tail call void @llvm.assume(i1 %cmp)302 %cond = icmp ugt i32 %cc, 1303 %res = select i1 %cond, i64 %x, i64 %y304 ret i64 %res305}306 307; Test-2(f2_1_*/f2_2_*/f2_3_*/f2_4_*).308; Both TrueVal and FalseVal are non-const with mixed patterns involving309; Binary Ops.310 311; Check 'add' for (cc != 0).312define i64 @f2_1_1(i64 %x, i64 %y, ptr %a) {313; CHECK-LABEL: f2_1_1:314; CHECK: # %bb.0: # %entry315; CHECK-NEXT: #APP316; CHECK-NEXT: alsi 0(%r4), -1317; CHECK-EMPTY:318; CHECK-NEXT: #NO_APP319; CHECK-NEXT: bner %r14320; CHECK-NEXT: .LBB14_1: # %entry321; CHECK-NEXT: lgr %r2, %r3322; CHECK-NEXT: br %r14323entry:324 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)325 %tmp = icmp ult i32 %cc, 4326 tail call void @llvm.assume(i1 %tmp)327 %add = add nsw i32 %cc, -1328 %cond = icmp ult i32 %add, 3329 %res = select i1 %cond, i64 %x, i64 %y330 ret i64 %res331}332 333; Check 'add' for (cc == 1|2).334define i64 @f2_1_2(i64 %x, i64 %y, ptr %a) {335; CHECK-LABEL: f2_1_2:336; CHECK: # %bb.0: # %entry337; CHECK-NEXT: #APP338; CHECK-NEXT: alsi 0(%r4), -1339; CHECK-EMPTY:340; CHECK-NEXT: #NO_APP341; CHECK-NEXT: blhr %r14342; CHECK-NEXT: .LBB15_1: # %entry343; CHECK-NEXT: lgr %r2, %r3344; CHECK-NEXT: br %r14345entry:346 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)347 %tmp = icmp ult i32 %cc, 4348 tail call void @llvm.assume(i1 %tmp)349 %add = add nsw i32 %cc, -1350 %cond = icmp ult i32 %add, 2351 %res = select i1 %cond, i64 %x, i64 %y352 ret i64 %res353}354 355; Check 'add' for (cc == 1|2).356define i64 @f2_1_3(i64 %y, i64 %x, ptr %a) {357; CHECK-LABEL: f2_1_3:358; CHECK: # %bb.0: # %entry359; CHECK-NEXT: #APP360; CHECK-NEXT: alsi 0(%r4), -1361; CHECK-EMPTY:362; CHECK-NEXT: #NO_APP363; CHECK-NEXT: bnlhr %r14364; CHECK-NEXT: .LBB16_1: # %entry365; CHECK-NEXT: lgr %r2, %r3366; CHECK-NEXT: br %r14367entry:368 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)369 %tmp = icmp ult i32 %cc, 4370 tail call void @llvm.assume(i1 %tmp)371 %add = add nsw i32 %cc, -3372 %cond.inv = icmp ult i32 %add, -2373 %res = select i1 %cond.inv, i64 %y, i64 %x374 ret i64 %res375}376 377; Check 'and' with one operand cc and other select_ccmask(cc !=1).378define i64 @f2_2_1(i64 %y, i64 %x, ptr %a) {379; CHECK-LABEL: f2_2_1:380; CHECK: # %bb.0: # %entry381; CHECK-NEXT: #APP382; CHECK-NEXT: alsi 0(%r4), -1383; CHECK-EMPTY:384; CHECK-NEXT: #NO_APP385; CHECK-NEXT: blr %r14386; CHECK-NEXT: .LBB17_1: # %entry387; CHECK-NEXT: lgr %r2, %r3388; CHECK-NEXT: br %r14389entry:390 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)391 %tmp = icmp ult i32 %cc, 4392 tail call void @llvm.assume(i1 %tmp)393 %andcc = and i32 %cc, 1394 %cmpne0 = icmp ne i32 %andcc, 0395 %cmpne3 = icmp ne i32 %cc, 3396 %cond.inv = and i1 %cmpne3, %cmpne0397 %res = select i1 %cond.inv, i64 %y, i64 %x398 ret i64 %res399}400 401; Check 'and' with both operands select_ccmask(cc != 2).402define i64 @f2_2_2(i64 %y, i64 %x, ptr %a) {403; CHECK-LABEL: f2_2_2:404; CHECK: # %bb.0: # %entry405; CHECK-NEXT: #APP406; CHECK-NEXT: alsi 0(%r4), -1407; CHECK-EMPTY:408; CHECK-NEXT: #NO_APP409; CHECK-NEXT: bhr %r14410; CHECK-NEXT: .LBB18_1: # %entry411; CHECK-NEXT: lgr %r2, %r3412; CHECK-NEXT: br %r14413entry:414 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)415 %tmp = icmp ult i32 %cc, 4416 tail call void @llvm.assume(i1 %tmp)417 %ugt1 = icmp samesign ugt i32 %cc, 1418 %cmpne3 = icmp ne i32 %cc, 3419 %cond.inv = and i1 %ugt1, %cmpne3420 %res = select i1 %cond.inv, i64 %y, i64 %x421 ret i64 %res422}423 424; Check 'and/tm' for (cc == 0|2).425define i64 @f2_2_3(i64 %x, i64 %y, ptr %a) {426; CHECK-LABEL: f2_2_3:427; CHECK: # %bb.0: # %entry428; CHECK-NEXT: #APP429; CHECK-NEXT: alsi 0(%r4), -1430; CHECK-EMPTY:431; CHECK-NEXT: #NO_APP432; CHECK-NEXT: bher %r14433; CHECK-NEXT: .LBB19_1: # %entry434; CHECK-NEXT: lgr %r2, %r3435; CHECK-NEXT: br %r14436entry:437 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)438 %tmp = icmp ult i32 %cc, 4439 tail call void @llvm.assume(i1 %tmp)440 %and = and i32 %cc, 1441 %cond = icmp eq i32 %and, 0442 %res = select i1 %cond, i64 %x, i64 %y443 ret i64 %res444}445 446; Check 'and/tm' for (cc == 1|3).447define i64 @f2_2_4(i64 %y, i64 %x, ptr %a) {448; CHECK-LABEL: f2_2_4:449; CHECK: # %bb.0: # %entry450; CHECK-NEXT: #APP451; CHECK-NEXT: alsi 0(%r4), -1452; CHECK-EMPTY:453; CHECK-NEXT: #NO_APP454; CHECK-NEXT: bher %r14455; CHECK-NEXT: .LBB20_1: # %entry456; CHECK-NEXT: lgr %r2, %r3457; CHECK-NEXT: br %r14458entry:459 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)460 %tmp = icmp ult i32 %cc, 4461 tail call void @llvm.assume(i1 %tmp)462 %and = and i32 %cc, 1463 %cond.inv = icmp eq i32 %and, 0464 %res = select i1 %cond.inv, i64 %y, i64 %x465 ret i64 %res466}467 468; Check 'icmp' with one operand 'and' and other 'select_ccmask'(cc != 1).469define i64 @f2_2_5(i64 %x, i64 %y, ptr %a) {470; CHECK-LABEL: f2_2_5:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: #APP473; CHECK-NEXT: alsi 0(%r4), -1474; CHECK-EMPTY:475; CHECK-NEXT: #NO_APP476; CHECK-NEXT: bnlr %r14477; CHECK-NEXT: .LBB21_1: # %entry478; CHECK-NEXT: lgr %r2, %r3479; CHECK-NEXT: br %r14480entry:481 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)482 %tmp = icmp ult i32 %cc, 4483 tail call void @llvm.assume(i1 %tmp)484 %trunc = trunc i32 %cc to i1485 %cmpne3 = icmp ne i32 %cc, 3486 %cond = xor i1 %cmpne3, %trunc487 %res = select i1 %cond, i64 %x, i64 %y488 ret i64 %res489}490 491 492; Check nested 'xor' cc with select_ccmask(cc != 1).493define i64 @f2_3_1(i64 %y, i64 %x, ptr %a) {494; CHECK-LABEL: f2_3_1:495; CHECK: # %bb.0: # %entry496; CHECK-NEXT: #APP497; CHECK-NEXT: alsi 0(%r4), -1498; CHECK-EMPTY:499; CHECK-NEXT: #NO_APP500; CHECK-NEXT: blr %r14501; CHECK-NEXT: .LBB22_1: # %entry502; CHECK-NEXT: lgr %r2, %r3503; CHECK-NEXT: br %r14504entry:505 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)506 %tmp = icmp ult i32 %cc, 4507 tail call void @llvm.assume(i1 %tmp)508 %cmpeq0 = icmp eq i32 %cc, 0509 %cmpeq2 = icmp eq i32 %cc, 2510 %xor = xor i1 %cmpeq0, %cmpeq2511 %cmpne3 = icmp ne i32 %cc, 3512 %cond.inv = xor i1 %cmpne3, %xor513 %res = select i1 %cond.inv, i64 %y, i64 %x514 ret i64 %res515}516 517; Check branching on 'tm' and 'xor' with one operand cc and the other518; select_ccmask(cc !=1).519define i64 @f2_3_2(i64 %y, i64 %x, ptr %a) {520; CHECK-LABEL: f2_3_2:521; CHECK: # %bb.0: # %entry522; CHECK-NEXT: #APP523; CHECK-NEXT: alsi 0(%r4), -1524; CHECK-EMPTY:525; CHECK-NEXT: #NO_APP526; CHECK-NEXT: blr %r14527; CHECK-NEXT: .LBB23_1: # %entry528; CHECK-NEXT: lgr %r2, %r3529; CHECK-NEXT: br %r14530entry:531 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)532 %tmp = icmp ult i32 %cc, 4533 tail call void @llvm.assume(i1 %tmp)534 %trunc = trunc i32 %cc to i1535 %cmpeq3 = icmp eq i32 %cc, 3536 %cond.inv = xor i1 %cmpeq3, %trunc537 %res = select i1 %cond.inv, i64 %y, i64 %x538 ret i64 %res539}540 541; Check branching on 'tm' and 'xor' with one operand cc and the other542; select_ccmask(cc !=2).543define i64 @f2_3_3(i64 %y, i64 %x, ptr %a) {544; CHECK-LABEL: f2_3_3:545; CHECK: # %bb.0: # %entry546; CHECK-NEXT: #APP547; CHECK-NEXT: alsi 0(%r4), -1548; CHECK-EMPTY:549; CHECK-NEXT: #NO_APP550; CHECK-NEXT: bhr %r14551; CHECK-NEXT: .LBB24_1: # %entry552; CHECK-NEXT: lgr %r2, %r3553; CHECK-NEXT: br %r14554entry:555 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)556 %tmp = icmp ult i32 %cc, 4557 tail call void @llvm.assume(i1 %tmp)558 %trunc = trunc i32 %cc to i1559 %cmpne0 = icmp ne i32 %cc, 0560 %cond.inv = xor i1 %cmpne0, %trunc561 %res = select i1 %cond.inv, i64 %y, i64 %x562 ret i64 %res563}564 565; Check 'or' with both operands select_ccmask with TM and ICMP(cc == 1).566define i64 @f2_4_1(i64 %y, i64 %x, ptr %a) {567; CHECK-LABEL: f2_4_1:568; CHECK: # %bb.0: # %entry569; CHECK-NEXT: #APP570; CHECK-NEXT: alsi 0(%r4), -1571; CHECK-EMPTY:572; CHECK-NEXT: #NO_APP573; CHECK-NEXT: bnlr %r14574; CHECK-NEXT: .LBB25_1: # %entry575; CHECK-NEXT: lgr %r2, %r3576; CHECK-NEXT: br %r14577entry:578 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)579 %tmp = icmp ult i32 %cc, 4580 tail call void @llvm.assume(i1 %tmp)581 %andcc = and i32 %cc, 1582 %cmpeq0 = icmp eq i32 %andcc, 0583 %cmpeq3 = icmp eq i32 %cc, 3584 %cond.inv = or i1 %cmpeq3, %cmpeq0585 %res = select i1 %cond.inv, i64 %y, i64 %x586 ret i64 %res587}588 589; Check 'or' for (cc == 0|1).590define i64 @f2_4_2(i64 %y, i64 %x, ptr %a) {591; CHECK-LABEL: f2_4_2:592; CHECK: # %bb.0: # %entry593; CHECK-NEXT: #APP594; CHECK-NEXT: alsi 0(%r4), -1595; CHECK-EMPTY:596; CHECK-NEXT: #NO_APP597; CHECK-NEXT: bnler %r14598; CHECK-NEXT: .LBB26_1: # %entry599; CHECK-NEXT: lgr %r2, %r3600; CHECK-NEXT: br %r14601entry:602 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)603 %tmp = icmp ult i32 %cc, 4604 tail call void @llvm.assume(i1 %tmp)605 %or = or disjoint i32 %cc, -4606 %cond.inv = icmp samesign ugt i32 %or, -3607 %res = select i1 %cond.inv, i64 %y, i64 %x608 ret i64 %res609}610 611; Check 'or' for (cc == 0|1).612define i64 @f2_4_3(i64 %x, i64 %y, ptr %a) {613; CHECK-LABEL: f2_4_3:614; CHECK: # %bb.0: # %entry615; CHECK-NEXT: #APP616; CHECK-NEXT: alsi 0(%r4), -1617; CHECK-EMPTY:618; CHECK-NEXT: #NO_APP619; CHECK-NEXT: bler %r14620; CHECK-NEXT: .LBB27_1: # %entry621; CHECK-NEXT: lgr %r2, %r3622; CHECK-NEXT: br %r14623entry:624 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)625 %tmp = icmp ult i32 %cc, 4626 tail call void @llvm.assume(i1 %tmp)627 %or = or disjoint i32 %cc, -4628 %cond = icmp samesign ult i32 %or, -2629 %res = select i1 %cond, i64 %x, i64 %y630 ret i64 %res631}632 633; Test-3(f3_1_*/f3_2_*/f3_3_*/f3_4_*).634; TrueVal is non-const and FalseVal is const with mixed patterns involving635; Binary Ops.636 637; Check 'add' for (cc != 0).638define i64 @f3_1_1(i64 %x, ptr %a) {639; CHECK-LABEL: f3_1_1:640; CHECK: # %bb.0: # %entry641; CHECK-NEXT: #APP642; CHECK-NEXT: alsi 0(%r3), -1643; CHECK-EMPTY:644; CHECK-NEXT: #NO_APP645; CHECK-NEXT: bner %r14646; CHECK-NEXT: .LBB28_1: # %entry647; CHECK-NEXT: lghi %r2, 5648; CHECK-NEXT: br %r14649entry:650 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)651 %tmp = icmp ult i32 %cc, 4652 tail call void @llvm.assume(i1 %tmp)653 %add = add nsw i32 %cc, -1654 %cond = icmp ult i32 %add, 3655 %res = select i1 %cond, i64 %x, i64 5656 ret i64 %res657}658 659; Check 'add' for (cc == 1|2).660define i64 @f3_1_2(i64 %x, ptr %a) {661; CHECK-LABEL: f3_1_2:662; CHECK: # %bb.0: # %entry663; CHECK-NEXT: #APP664; CHECK-NEXT: alsi 0(%r3), -1665; CHECK-EMPTY:666; CHECK-NEXT: #NO_APP667; CHECK-NEXT: blhr %r14668; CHECK-NEXT: .LBB29_1: # %entry669; CHECK-NEXT: lghi %r2, 5670; CHECK-NEXT: br %r14671entry:672 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)673 %tmp = icmp ult i32 %cc, 4674 tail call void @llvm.assume(i1 %tmp)675 %add = add nsw i32 %cc, -1676 %cond = icmp ult i32 %add, 2677 %res = select i1 %cond, i64 %x, i64 5678 ret i64 %res679}680 681; Check 'add' for (cc == 1|2).682define i64 @f3_1_3(ptr %a, i64 %x) {683; CHECK-LABEL: f3_1_3:684; CHECK: # %bb.0: # %entry685; CHECK-NEXT: #APP686; CHECK-NEXT: alsi 0(%r2), -1687; CHECK-EMPTY:688; CHECK-NEXT: #NO_APP689; CHECK-NEXT: lghi %r2, 5690; CHECK-NEXT: bnlhr %r14691; CHECK-NEXT: .LBB30_1: # %entry692; CHECK-NEXT: lgr %r2, %r3693; CHECK-NEXT: br %r14694entry:695 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)696 %tmp = icmp ult i32 %cc, 4697 tail call void @llvm.assume(i1 %tmp)698 %add = add nsw i32 %cc, -3699 %cond.inv = icmp ult i32 %add, -2700 %res = select i1 %cond.inv, i64 5, i64 %x701 ret i64 %res702}703 704; Check 'and' with one operand cc and other select_ccmask(cc !=1).705define i64 @f3_2_1(ptr %a, i64 %x) {706; CHECK-LABEL: f3_2_1:707; CHECK: # %bb.0: # %entry708; CHECK-NEXT: #APP709; CHECK-NEXT: alsi 0(%r2), -1710; CHECK-EMPTY:711; CHECK-NEXT: #NO_APP712; CHECK-NEXT: lghi %r2, 5713; CHECK-NEXT: blr %r14714; CHECK-NEXT: .LBB31_1: # %entry715; CHECK-NEXT: lgr %r2, %r3716; CHECK-NEXT: br %r14717entry:718 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)719 %tmp = icmp ult i32 %cc, 4720 tail call void @llvm.assume(i1 %tmp)721 %andcc = and i32 %cc, 1722 %cmpne0 = icmp ne i32 %andcc, 0723 %cmpne3 = icmp ne i32 %cc, 3724 %cond.inv = and i1 %cmpne3, %cmpne0725 %res = select i1 %cond.inv, i64 5, i64 %x726 ret i64 %res727}728 729; Check 'and' with both operands select_ccmask(cc != 2).730define i64 @f3_2_2(ptr %a, i64 %x) {731; CHECK-LABEL: f3_2_2:732; CHECK: # %bb.0: # %entry733; CHECK-NEXT: #APP734; CHECK-NEXT: alsi 0(%r2), -1735; CHECK-EMPTY:736; CHECK-NEXT: #NO_APP737; CHECK-NEXT: lghi %r2, 5738; CHECK-NEXT: bhr %r14739; CHECK-NEXT: .LBB32_1: # %entry740; CHECK-NEXT: lgr %r2, %r3741; CHECK-NEXT: br %r14742entry:743 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)744 %tmp = icmp ult i32 %cc, 4745 tail call void @llvm.assume(i1 %tmp)746 %ugt1 = icmp samesign ugt i32 %cc, 1747 %cmpne3 = icmp ne i32 %cc, 3748 %cond.inv = and i1 %ugt1, %cmpne3749 %res = select i1 %cond.inv, i64 5, i64 %x750 ret i64 %res751}752 753; Check 'and/tm' for (cc == 0|2).754define i64 @f3_2_3(i64 %x, ptr %a) {755; CHECK-LABEL: f3_2_3:756; CHECK: # %bb.0: # %entry757; CHECK-NEXT: #APP758; CHECK-NEXT: alsi 0(%r3), -1759; CHECK-EMPTY:760; CHECK-NEXT: #NO_APP761; CHECK-NEXT: bher %r14762; CHECK-NEXT: .LBB33_1: # %entry763; CHECK-NEXT: lghi %r2, 5764; CHECK-NEXT: br %r14765entry:766 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)767 %tmp = icmp ult i32 %cc, 4768 tail call void @llvm.assume(i1 %tmp)769 %and = and i32 %cc, 1770 %cond = icmp eq i32 %and, 0771 %res = select i1 %cond, i64 %x, i64 5772 ret i64 %res773}774 775; Check 'and/tm' for (cc == 1|3).776define i64 @f3_2_4(ptr %a, i64 %x) {777; CHECK-LABEL: f3_2_4:778; CHECK: # %bb.0: # %entry779; CHECK-NEXT: #APP780; CHECK-NEXT: alsi 0(%r2), -1781; CHECK-EMPTY:782; CHECK-NEXT: #NO_APP783; CHECK-NEXT: lghi %r2, 5784; CHECK-NEXT: bher %r14785; CHECK-NEXT: .LBB34_1: # %entry786; CHECK-NEXT: lgr %r2, %r3787; CHECK-NEXT: br %r14788entry:789 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)790 %tmp = icmp ult i32 %cc, 4791 tail call void @llvm.assume(i1 %tmp)792 %and = and i32 %cc, 1793 %cond.inv = icmp eq i32 %and, 0794 %res = select i1 %cond.inv, i64 5, i64 %x795 ret i64 %res796}797 798; Check 'icmp' with one operand 'and' and other 'select_ccmask'(cc != 1).799define i64 @f3_2_5(i64 %x, ptr %a) {800; CHECK-LABEL: f3_2_5:801; CHECK: # %bb.0: # %entry802; CHECK-NEXT: #APP803; CHECK-NEXT: alsi 0(%r3), -1804; CHECK-EMPTY:805; CHECK-NEXT: #NO_APP806; CHECK-NEXT: bnlr %r14807; CHECK-NEXT: .LBB35_1: # %entry808; CHECK-NEXT: lghi %r2, 5809; CHECK-NEXT: br %r14810entry:811 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)812 %tmp = icmp ult i32 %cc, 4813 tail call void @llvm.assume(i1 %tmp)814 %trunc = trunc i32 %cc to i1815 %cmpne3 = icmp ne i32 %cc, 3816 %cond = xor i1 %cmpne3, %trunc817 %res = select i1 %cond, i64 %x, i64 5818 ret i64 %res819}820 821 822; Check nested 'xor' cc with select_ccmask(cc != 1).823define i64 @f3_3_1(ptr %a, i64 %x) {824; CHECK-LABEL: f3_3_1:825; CHECK: # %bb.0: # %entry826; CHECK-NEXT: #APP827; CHECK-NEXT: alsi 0(%r2), -1828; CHECK-EMPTY:829; CHECK-NEXT: #NO_APP830; CHECK-NEXT: lghi %r2, 5831; CHECK-NEXT: blr %r14832; CHECK-NEXT: .LBB36_1: # %entry833; CHECK-NEXT: lgr %r2, %r3834; CHECK-NEXT: br %r14835entry:836 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)837 %tmp = icmp ult i32 %cc, 4838 tail call void @llvm.assume(i1 %tmp)839 %cmpeq0 = icmp eq i32 %cc, 0840 %cmpeq2 = icmp eq i32 %cc, 2841 %xor = xor i1 %cmpeq0, %cmpeq2842 %cmpne3 = icmp ne i32 %cc, 3843 %cond.inv = xor i1 %cmpne3, %xor844 %res = select i1 %cond.inv, i64 5, i64 %x845 ret i64 %res846}847 848; Check branching on 'tm' and 'xor' with one operand cc and the other849; select_ccmask(cc !=1).850define i64 @f3_3_2(ptr %a, i64 %x) {851; CHECK-LABEL: f3_3_2:852; CHECK: # %bb.0: # %entry853; CHECK-NEXT: #APP854; CHECK-NEXT: alsi 0(%r2), -1855; CHECK-EMPTY:856; CHECK-NEXT: #NO_APP857; CHECK-NEXT: lghi %r2, 5858; CHECK-NEXT: blr %r14859; CHECK-NEXT: .LBB37_1: # %entry860; CHECK-NEXT: lgr %r2, %r3861; CHECK-NEXT: br %r14862entry:863 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)864 %tmp = icmp ult i32 %cc, 4865 tail call void @llvm.assume(i1 %tmp)866 %trunc = trunc i32 %cc to i1867 %cmpeq3 = icmp eq i32 %cc, 3868 %cond.inv = xor i1 %cmpeq3, %trunc869 %res = select i1 %cond.inv, i64 5, i64 %x870 ret i64 %res871}872 873; Check branching on 'tm' and 'xor' with one operand cc and the other874; select_ccmask(cc !=2).875define i64 @f3_3_3(ptr %a, i64 %x) {876; CHECK-LABEL: f3_3_3:877; CHECK: # %bb.0: # %entry878; CHECK-NEXT: #APP879; CHECK-NEXT: alsi 0(%r2), -1880; CHECK-EMPTY:881; CHECK-NEXT: #NO_APP882; CHECK-NEXT: lghi %r2, 5883; CHECK-NEXT: bhr %r14884; CHECK-NEXT: .LBB38_1: # %entry885; CHECK-NEXT: lgr %r2, %r3886; CHECK-NEXT: br %r14887entry:888 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)889 %tmp = icmp ult i32 %cc, 4890 tail call void @llvm.assume(i1 %tmp)891 %trunc = trunc i32 %cc to i1892 %cmpne0 = icmp ne i32 %cc, 0893 %cond.inv = xor i1 %cmpne0, %trunc894 %res = select i1 %cond.inv, i64 5, i64 %x895 ret i64 %res896}897 898; Check 'or' with both operands select_ccmask with TM and ICMP(cc == 1).899define i64 @f3_4_1(ptr %a, i64 %x) {900; CHECK-LABEL: f3_4_1:901; CHECK: # %bb.0: # %entry902; CHECK-NEXT: #APP903; CHECK-NEXT: alsi 0(%r2), -1904; CHECK-EMPTY:905; CHECK-NEXT: #NO_APP906; CHECK-NEXT: lghi %r2, 5907; CHECK-NEXT: bnlr %r14908; CHECK-NEXT: .LBB39_1: # %entry909; CHECK-NEXT: lgr %r2, %r3910; CHECK-NEXT: br %r14911entry:912 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)913 %tmp = icmp ult i32 %cc, 4914 tail call void @llvm.assume(i1 %tmp)915 %andcc = and i32 %cc, 1916 %cmpeq0 = icmp eq i32 %andcc, 0917 %cmpeq3 = icmp eq i32 %cc, 3918 %cond.inv = or i1 %cmpeq3, %cmpeq0919 %res = select i1 %cond.inv, i64 5, i64 %x920 ret i64 %res921}922 923; Check 'or' for (cc == 0|1).924define i64 @f3_4_2(ptr %a, i64 %x) {925; CHECK-LABEL: f3_4_2:926; CHECK: # %bb.0: # %entry927; CHECK-NEXT: #APP928; CHECK-NEXT: alsi 0(%r2), -1929; CHECK-EMPTY:930; CHECK-NEXT: #NO_APP931; CHECK-NEXT: lghi %r2, 5932; CHECK-NEXT: bnler %r14933; CHECK-NEXT: .LBB40_1: # %entry934; CHECK-NEXT: lgr %r2, %r3935; CHECK-NEXT: br %r14936entry:937 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)938 %tmp = icmp ult i32 %cc, 4939 tail call void @llvm.assume(i1 %tmp)940 %or = or disjoint i32 %cc, -4941 %cond.inv = icmp samesign ugt i32 %or, -3942 %res = select i1 %cond.inv, i64 5, i64 %x943 ret i64 %res944}945 946; Check 'or' for (cc == 0|1).947define i64 @f3_4_3(i64 %x, ptr %a) {948; CHECK-LABEL: f3_4_3:949; CHECK: # %bb.0: # %entry950; CHECK-NEXT: #APP951; CHECK-NEXT: alsi 0(%r3), -1952; CHECK-EMPTY:953; CHECK-NEXT: #NO_APP954; CHECK-NEXT: bler %r14955; CHECK-NEXT: .LBB41_1: # %entry956; CHECK-NEXT: lghi %r2, 5957; CHECK-NEXT: br %r14958entry:959 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)960 %tmp = icmp ult i32 %cc, 4961 tail call void @llvm.assume(i1 %tmp)962 %or = or disjoint i32 %cc, -4963 %cond = icmp samesign ult i32 %or, -2964 %res = select i1 %cond, i64 %x, i64 5965 ret i64 %res966}967 968 969; Test-4(f4_1_*/f4_2_*/f4_3_*/f4_4_*).970; TrueVal is const and FalseVal is non-const with mixed patterns involving971; Binary Ops.972 973; Check 'add' for (cc != 0).974define i64 @f4_1_1(ptr %a, i64 %y) {975; CHECK-LABEL: f4_1_1:976; CHECK: # %bb.0: # %entry977; CHECK-NEXT: #APP978; CHECK-NEXT: alsi 0(%r2), -1979; CHECK-EMPTY:980; CHECK-NEXT: #NO_APP981; CHECK-NEXT: lghi %r2, 15982; CHECK-NEXT: bner %r14983; CHECK-NEXT: .LBB42_1: # %entry984; CHECK-NEXT: lgr %r2, %r3985; CHECK-NEXT: br %r14986entry:987 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)988 %tmp = icmp ult i32 %cc, 4989 tail call void @llvm.assume(i1 %tmp)990 %add = add nsw i32 %cc, -1991 %cond = icmp ult i32 %add, 3992 %res = select i1 %cond, i64 15, i64 %y993 ret i64 %res994}995 996; Check 'add' for (cc == 1|2).997define i64 @f4_1_2(ptr %a, i64 %y) {998; CHECK-LABEL: f4_1_2:999; CHECK: # %bb.0: # %entry1000; CHECK-NEXT: #APP1001; CHECK-NEXT: alsi 0(%r2), -11002; CHECK-EMPTY:1003; CHECK-NEXT: #NO_APP1004; CHECK-NEXT: lghi %r2, 151005; CHECK-NEXT: blhr %r141006; CHECK-NEXT: .LBB43_1: # %entry1007; CHECK-NEXT: lgr %r2, %r31008; CHECK-NEXT: br %r141009entry:1010 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1011 %tmp = icmp ult i32 %cc, 41012 tail call void @llvm.assume(i1 %tmp)1013 %add = add nsw i32 %cc, -11014 %cond = icmp ult i32 %add, 21015 %res = select i1 %cond, i64 15, i64 %y1016 ret i64 %res1017}1018 1019; Check 'add' for (cc == 1|2).1020define i64 @f4_1_3(i64 %y, ptr %a) {1021; CHECK-LABEL: f4_1_3:1022; CHECK: # %bb.0: # %entry1023; CHECK-NEXT: #APP1024; CHECK-NEXT: alsi 0(%r3), -11025; CHECK-EMPTY:1026; CHECK-NEXT: #NO_APP1027; CHECK-NEXT: bnlhr %r141028; CHECK-NEXT: .LBB44_1: # %entry1029; CHECK-NEXT: lghi %r2, 151030; CHECK-NEXT: br %r141031entry:1032 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1033 %tmp = icmp ult i32 %cc, 41034 tail call void @llvm.assume(i1 %tmp)1035 %add = add nsw i32 %cc, -31036 %cond.inv = icmp ult i32 %add, -21037 %res = select i1 %cond.inv, i64 %y, i64 151038 ret i64 %res1039}1040 1041; Check 'and' with one operand cc and other select_ccmask(cc !=1).1042define i64 @f4_2_1(i64 %y, ptr %a) {1043; CHECK-LABEL: f4_2_1:1044; CHECK: # %bb.0: # %entry1045; CHECK-NEXT: #APP1046; CHECK-NEXT: alsi 0(%r3), -11047; CHECK-EMPTY:1048; CHECK-NEXT: #NO_APP1049; CHECK-NEXT: blr %r141050; CHECK-NEXT: .LBB45_1: # %entry1051; CHECK-NEXT: lghi %r2, 151052; CHECK-NEXT: br %r141053entry:1054 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1055 %tmp = icmp ult i32 %cc, 41056 tail call void @llvm.assume(i1 %tmp)1057 %andcc = and i32 %cc, 11058 %cmpne0 = icmp ne i32 %andcc, 01059 %cmpne3 = icmp ne i32 %cc, 31060 %cond.inv = and i1 %cmpne3, %cmpne01061 %res = select i1 %cond.inv, i64 %y, i64 151062 ret i64 %res1063}1064 1065; Check 'and' with both operands select_ccmask(cc != 2).1066define i64 @f4_2_2(i64 %y, ptr %a) {1067; CHECK-LABEL: f4_2_2:1068; CHECK: # %bb.0: # %entry1069; CHECK-NEXT: #APP1070; CHECK-NEXT: alsi 0(%r3), -11071; CHECK-EMPTY:1072; CHECK-NEXT: #NO_APP1073; CHECK-NEXT: bhr %r141074; CHECK-NEXT: .LBB46_1: # %entry1075; CHECK-NEXT: lghi %r2, 151076; CHECK-NEXT: br %r141077entry:1078 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1079 %tmp = icmp ult i32 %cc, 41080 tail call void @llvm.assume(i1 %tmp)1081 %ugt1 = icmp samesign ugt i32 %cc, 11082 %cmpne3 = icmp ne i32 %cc, 31083 %cond.inv = and i1 %ugt1, %cmpne31084 %res = select i1 %cond.inv, i64 %y, i64 151085 ret i64 %res1086}1087 1088; Check 'and/tm' for (cc == 0|2).1089define i64 @f4_2_3(ptr %a, i64 %y) {1090; CHECK-LABEL: f4_2_3:1091; CHECK: # %bb.0: # %entry1092; CHECK-NEXT: #APP1093; CHECK-NEXT: alsi 0(%r2), -11094; CHECK-EMPTY:1095; CHECK-NEXT: #NO_APP1096; CHECK-NEXT: lghi %r2, 151097; CHECK-NEXT: bher %r141098; CHECK-NEXT: .LBB47_1: # %entry1099; CHECK-NEXT: lgr %r2, %r31100; CHECK-NEXT: br %r141101entry:1102 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1103 %tmp = icmp ult i32 %cc, 41104 tail call void @llvm.assume(i1 %tmp)1105 %and = and i32 %cc, 11106 %cond = icmp eq i32 %and, 01107 %res = select i1 %cond, i64 15, i64 %y1108 ret i64 %res1109}1110 1111; Check 'and/tm' for (cc == 1|3).1112define i64 @f4_2_4(i64 %y, ptr %a) {1113; CHECK-LABEL: f4_2_4:1114; CHECK: # %bb.0: # %entry1115; CHECK-NEXT: #APP1116; CHECK-NEXT: alsi 0(%r3), -11117; CHECK-EMPTY:1118; CHECK-NEXT: #NO_APP1119; CHECK-NEXT: bher %r141120; CHECK-NEXT: .LBB48_1: # %entry1121; CHECK-NEXT: lghi %r2, 151122; CHECK-NEXT: br %r141123entry:1124 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1125 %tmp = icmp ult i32 %cc, 41126 tail call void @llvm.assume(i1 %tmp)1127 %and = and i32 %cc, 11128 %cond.inv = icmp eq i32 %and, 01129 %res = select i1 %cond.inv, i64 %y, i64 151130 ret i64 %res1131}1132 1133; Check 'icmp' with one operand 'and' and other 'select_ccmask'(cc != 1).1134define i64 @f4_2_5(ptr %a, i64 %y) {1135; CHECK-LABEL: f4_2_5:1136; CHECK: # %bb.0: # %entry1137; CHECK-NEXT: #APP1138; CHECK-NEXT: alsi 0(%r2), -11139; CHECK-EMPTY:1140; CHECK-NEXT: #NO_APP1141; CHECK-NEXT: lghi %r2, 151142; CHECK-NEXT: bnlr %r141143; CHECK-NEXT: .LBB49_1: # %entry1144; CHECK-NEXT: lgr %r2, %r31145; CHECK-NEXT: br %r141146entry:1147 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1148 %tmp = icmp ult i32 %cc, 41149 tail call void @llvm.assume(i1 %tmp)1150 %trunc = trunc i32 %cc to i11151 %cmpne3 = icmp ne i32 %cc, 31152 %cond = xor i1 %cmpne3, %trunc1153 %res = select i1 %cond, i64 15, i64 %y1154 ret i64 %res1155}1156 1157 1158; Check nested 'xor' cc with select_ccmask(cc != 1).1159define i64 @f4_3_1(i64 %y, ptr %a) {1160; CHECK-LABEL: f4_3_1:1161; CHECK: # %bb.0: # %entry1162; CHECK-NEXT: #APP1163; CHECK-NEXT: alsi 0(%r3), -11164; CHECK-EMPTY:1165; CHECK-NEXT: #NO_APP1166; CHECK-NEXT: blr %r141167; CHECK-NEXT: .LBB50_1: # %entry1168; CHECK-NEXT: lghi %r2, 151169; CHECK-NEXT: br %r141170entry:1171 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1172 %tmp = icmp ult i32 %cc, 41173 tail call void @llvm.assume(i1 %tmp)1174 %cmpeq0 = icmp eq i32 %cc, 01175 %cmpeq2 = icmp eq i32 %cc, 21176 %xor = xor i1 %cmpeq0, %cmpeq21177 %cmpne3 = icmp ne i32 %cc, 31178 %cond.inv = xor i1 %cmpne3, %xor1179 %res = select i1 %cond.inv, i64 %y, i64 151180 ret i64 %res1181}1182 1183; Check branching on 'tm' and 'xor' with one operand cc and the other1184; select_ccmask(cc !=1).1185define i64 @f4_3_2(i64 %y, ptr %a) {1186; CHECK-LABEL: f4_3_2:1187; CHECK: # %bb.0: # %entry1188; CHECK-NEXT: #APP1189; CHECK-NEXT: alsi 0(%r3), -11190; CHECK-EMPTY:1191; CHECK-NEXT: #NO_APP1192; CHECK-NEXT: blr %r141193; CHECK-NEXT: .LBB51_1: # %entry1194; CHECK-NEXT: lghi %r2, 151195; CHECK-NEXT: br %r141196entry:1197 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1198 %tmp = icmp ult i32 %cc, 41199 tail call void @llvm.assume(i1 %tmp)1200 %trunc = trunc i32 %cc to i11201 %cmpeq3 = icmp eq i32 %cc, 31202 %cond.inv = xor i1 %cmpeq3, %trunc1203 %res = select i1 %cond.inv, i64 %y, i64 151204 ret i64 %res1205}1206 1207; Check branching on 'tm' and 'xor' with one operand cc and the other1208; select_ccmask(cc !=2).1209define i64 @f4_3_3(i64 %y, ptr %a) {1210; CHECK-LABEL: f4_3_3:1211; CHECK: # %bb.0: # %entry1212; CHECK-NEXT: #APP1213; CHECK-NEXT: alsi 0(%r3), -11214; CHECK-EMPTY:1215; CHECK-NEXT: #NO_APP1216; CHECK-NEXT: bhr %r141217; CHECK-NEXT: .LBB52_1: # %entry1218; CHECK-NEXT: lghi %r2, 151219; CHECK-NEXT: br %r141220entry:1221 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1222 %tmp = icmp ult i32 %cc, 41223 tail call void @llvm.assume(i1 %tmp)1224 %trunc = trunc i32 %cc to i11225 %cmpne0 = icmp ne i32 %cc, 01226 %cond.inv = xor i1 %cmpne0, %trunc1227 %res = select i1 %cond.inv, i64 %y, i64 151228 ret i64 %res1229}1230 1231; Check 'or' with both operands select_ccmask with TM and ICMP(cc == 1).1232define i64 @f4_4_1(i64 %y,ptr %a) {1233; CHECK-LABEL: f4_4_1:1234; CHECK: # %bb.0: # %entry1235; CHECK-NEXT: #APP1236; CHECK-NEXT: alsi 0(%r3), -11237; CHECK-EMPTY:1238; CHECK-NEXT: #NO_APP1239; CHECK-NEXT: bnlr %r141240; CHECK-NEXT: .LBB53_1: # %entry1241; CHECK-NEXT: lghi %r2, 151242; CHECK-NEXT: br %r141243entry:1244 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1245 %tmp = icmp ult i32 %cc, 41246 tail call void @llvm.assume(i1 %tmp)1247 %andcc = and i32 %cc, 11248 %cmpeq0 = icmp eq i32 %andcc, 01249 %cmpeq3 = icmp eq i32 %cc, 31250 %cond.inv = or i1 %cmpeq3, %cmpeq01251 %res = select i1 %cond.inv, i64 %y, i64 151252 ret i64 %res1253}1254 1255; Check 'or' for (cc == 0|1).1256define i64 @f4_4_2(i64 %y, ptr %a) {1257; CHECK-LABEL: f4_4_2:1258; CHECK: # %bb.0: # %entry1259; CHECK-NEXT: #APP1260; CHECK-NEXT: alsi 0(%r3), -11261; CHECK-EMPTY:1262; CHECK-NEXT: #NO_APP1263; CHECK-NEXT: bnler %r141264; CHECK-NEXT: .LBB54_1: # %entry1265; CHECK-NEXT: lghi %r2, 151266; CHECK-NEXT: br %r141267entry:1268 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1269 %tmp = icmp ult i32 %cc, 41270 tail call void @llvm.assume(i1 %tmp)1271 %or = or disjoint i32 %cc, -41272 %cond.inv = icmp samesign ugt i32 %or, -31273 %res = select i1 %cond.inv, i64 %y, i64 151274 ret i64 %res1275}1276 1277; Check 'or' for (cc == 0|1).1278define i64 @f4_4_3(ptr %a, i64 %y) {1279; CHECK-LABEL: f4_4_3:1280; CHECK: # %bb.0: # %entry1281; CHECK-NEXT: #APP1282; CHECK-NEXT: alsi 0(%r2), -11283; CHECK-EMPTY:1284; CHECK-NEXT: #NO_APP1285; CHECK-NEXT: lghi %r2, 151286; CHECK-NEXT: bler %r141287; CHECK-NEXT: .LBB55_1: # %entry1288; CHECK-NEXT: lgr %r2, %r31289; CHECK-NEXT: br %r141290entry:1291 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1292 %tmp = icmp ult i32 %cc, 41293 tail call void @llvm.assume(i1 %tmp)1294 %or = or disjoint i32 %cc, -41295 %cond = icmp samesign ult i32 %or, -21296 %res = select i1 %cond, i64 15, i64 %y1297 ret i64 %res1298}1299 1300; Test-5(f5_1_*/f5_2_*/f5_3_*/f5_4_*).1301; Both TrueVal and FalseVal are const with mixed patterns involving1302; Binary Ops.1303 1304 1305; Check 'add' for (cc != 0).1306define i64 @f5_1_1(ptr %a) {1307; CHECK-LABEL: f5_1_1:1308; CHECK: # %bb.0: # %entry1309; CHECK-NEXT: #APP1310; CHECK-NEXT: alsi 0(%r2), -11311; CHECK-EMPTY:1312; CHECK-NEXT: #NO_APP1313; CHECK-NEXT: lghi %r2, 151314; CHECK-NEXT: bner %r141315; CHECK-NEXT: .LBB56_1: # %entry1316; CHECK-NEXT: lghi %r2, 51317; CHECK-NEXT: br %r141318entry:1319 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1320 %tmp = icmp ult i32 %cc, 41321 tail call void @llvm.assume(i1 %tmp)1322 %add = add nsw i32 %cc, -11323 %cond = icmp ult i32 %add, 31324 %res = select i1 %cond, i64 15, i64 51325 ret i64 %res1326}1327 1328; Check 'add' for (cc == 1|2).1329define i64 @f5_1_2(ptr %a) {1330; CHECK-LABEL: f5_1_2:1331; CHECK: # %bb.0: # %entry1332; CHECK-NEXT: #APP1333; CHECK-NEXT: alsi 0(%r2), -11334; CHECK-EMPTY:1335; CHECK-NEXT: #NO_APP1336; CHECK-NEXT: lghi %r2, 151337; CHECK-NEXT: blhr %r141338; CHECK-NEXT: .LBB57_1: # %entry1339; CHECK-NEXT: lghi %r2, 51340; CHECK-NEXT: br %r141341entry:1342 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1343 %tmp = icmp ult i32 %cc, 41344 tail call void @llvm.assume(i1 %tmp)1345 %add = add nsw i32 %cc, -11346 %cond = icmp ult i32 %add, 21347 %res = select i1 %cond, i64 15, i64 51348 ret i64 %res1349}1350 1351; Check 'add' for (cc == 1|2).1352define i64 @f5_1_3(ptr %a) {1353; CHECK-LABEL: f5_1_3:1354; CHECK: # %bb.0: # %entry1355; CHECK-NEXT: #APP1356; CHECK-NEXT: alsi 0(%r2), -11357; CHECK-EMPTY:1358; CHECK-NEXT: #NO_APP1359; CHECK-NEXT: lghi %r2, 51360; CHECK-NEXT: bnlhr %r141361; CHECK-NEXT: .LBB58_1: # %entry1362; CHECK-NEXT: lghi %r2, 151363; CHECK-NEXT: br %r141364entry:1365 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1366 %tmp = icmp ult i32 %cc, 41367 tail call void @llvm.assume(i1 %tmp)1368 %add = add nsw i32 %cc, -31369 %cond.inv = icmp ult i32 %add, -21370 %res = select i1 %cond.inv, i64 5, i64 151371 ret i64 %res1372}1373 1374; Check 'and' with one operand cc and other select_ccmask(cc !=1).1375define i64 @f5_2_1(ptr %a) {1376; CHECK-LABEL: f5_2_1:1377; CHECK: # %bb.0: # %entry1378; CHECK-NEXT: #APP1379; CHECK-NEXT: alsi 0(%r2), -11380; CHECK-EMPTY:1381; CHECK-NEXT: #NO_APP1382; CHECK-NEXT: lghi %r2, 51383; CHECK-NEXT: blr %r141384; CHECK-NEXT: .LBB59_1: # %entry1385; CHECK-NEXT: lghi %r2, 151386; CHECK-NEXT: br %r141387entry:1388 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1389 %tmp = icmp ult i32 %cc, 41390 tail call void @llvm.assume(i1 %tmp)1391 %andcc = and i32 %cc, 11392 %cmpne0 = icmp ne i32 %andcc, 01393 %cmpne3 = icmp ne i32 %cc, 31394 %cond.inv = and i1 %cmpne3, %cmpne01395 %res = select i1 %cond.inv, i64 5, i64 151396 ret i64 %res1397}1398 1399; Check 'and' with both operands select_ccmask(cc != 2).1400define i64 @f5_2_2(ptr %a) {1401; CHECK-LABEL: f5_2_2:1402; CHECK: # %bb.0: # %entry1403; CHECK-NEXT: #APP1404; CHECK-NEXT: alsi 0(%r2), -11405; CHECK-EMPTY:1406; CHECK-NEXT: #NO_APP1407; CHECK-NEXT: lghi %r2, 51408; CHECK-NEXT: bhr %r141409; CHECK-NEXT: .LBB60_1: # %entry1410; CHECK-NEXT: lghi %r2, 151411; CHECK-NEXT: br %r141412entry:1413 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1414 %tmp = icmp ult i32 %cc, 41415 tail call void @llvm.assume(i1 %tmp)1416 %ugt1 = icmp samesign ugt i32 %cc, 11417 %cmpne3 = icmp ne i32 %cc, 31418 %cond.inv = and i1 %ugt1, %cmpne31419 %res = select i1 %cond.inv, i64 5, i64 151420 ret i64 %res1421}1422 1423; Check 'and/tm' for (cc == 0|2).1424define i64 @f5_2_3(ptr %a) {1425; CHECK-LABEL: f5_2_3:1426; CHECK: # %bb.0: # %entry1427; CHECK-NEXT: #APP1428; CHECK-NEXT: alsi 0(%r2), -11429; CHECK-EMPTY:1430; CHECK-NEXT: #NO_APP1431; CHECK-NEXT: lghi %r2, 151432; CHECK-NEXT: bher %r141433; CHECK-NEXT: .LBB61_1: # %entry1434; CHECK-NEXT: lghi %r2, 51435; CHECK-NEXT: br %r141436entry:1437 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1438 %tmp = icmp ult i32 %cc, 41439 tail call void @llvm.assume(i1 %tmp)1440 %and = and i32 %cc, 11441 %cond = icmp eq i32 %and, 01442 %res = select i1 %cond, i64 15, i64 51443 ret i64 %res1444}1445 1446; Check 'and/tm' for (cc == 1|3).1447define i64 @f5_2_4(ptr %a) {1448; CHECK-LABEL: f5_2_4:1449; CHECK: # %bb.0: # %entry1450; CHECK-NEXT: #APP1451; CHECK-NEXT: alsi 0(%r2), -11452; CHECK-EMPTY:1453; CHECK-NEXT: #NO_APP1454; CHECK-NEXT: lghi %r2, 51455; CHECK-NEXT: bher %r141456; CHECK-NEXT: .LBB62_1: # %entry1457; CHECK-NEXT: lghi %r2, 151458; CHECK-NEXT: br %r141459entry:1460 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1461 %tmp = icmp ult i32 %cc, 41462 tail call void @llvm.assume(i1 %tmp)1463 %and = and i32 %cc, 11464 %cond.inv = icmp eq i32 %and, 01465 %res = select i1 %cond.inv, i64 5, i64 151466 ret i64 %res1467}1468 1469; Check 'icmp' with one operand 'and' and other 'select_ccmask'(cc != 1).1470define i64 @f5_2_5(ptr %a) {1471; CHECK-LABEL: f5_2_5:1472; CHECK: # %bb.0: # %entry1473; CHECK-NEXT: #APP1474; CHECK-NEXT: alsi 0(%r2), -11475; CHECK-EMPTY:1476; CHECK-NEXT: #NO_APP1477; CHECK-NEXT: lghi %r2, 151478; CHECK-NEXT: bnlr %r141479; CHECK-NEXT: .LBB63_1: # %entry1480; CHECK-NEXT: lghi %r2, 51481; CHECK-NEXT: br %r141482entry:1483 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1484 %tmp = icmp ult i32 %cc, 41485 tail call void @llvm.assume(i1 %tmp)1486 %trunc = trunc i32 %cc to i11487 %cmpne3 = icmp ne i32 %cc, 31488 %cond = xor i1 %cmpne3, %trunc1489 %res = select i1 %cond, i64 15, i64 51490 ret i64 %res1491}1492 1493 1494; Check nested 'xor' cc with select_ccmask(cc != 1).1495define i64 @f5_3_1(ptr %a) {1496; CHECK-LABEL: f5_3_1:1497; CHECK: # %bb.0: # %entry1498; CHECK-NEXT: #APP1499; CHECK-NEXT: alsi 0(%r2), -11500; CHECK-EMPTY:1501; CHECK-NEXT: #NO_APP1502; CHECK-NEXT: lghi %r2, 51503; CHECK-NEXT: blr %r141504; CHECK-NEXT: .LBB64_1: # %entry1505; CHECK-NEXT: lghi %r2, 151506; CHECK-NEXT: br %r141507entry:1508 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1509 %tmp = icmp ult i32 %cc, 41510 tail call void @llvm.assume(i1 %tmp)1511 %cmpeq0 = icmp eq i32 %cc, 01512 %cmpeq2 = icmp eq i32 %cc, 21513 %xor = xor i1 %cmpeq0, %cmpeq21514 %cmpne3 = icmp ne i32 %cc, 31515 %cond.inv = xor i1 %cmpne3, %xor1516 %res = select i1 %cond.inv, i64 5, i64 151517 ret i64 %res1518}1519 1520; Check branching on 'tm' and 'xor' with one operand cc and the other1521; select_ccmask(cc !=1).1522define i64 @f5_3_2(ptr %a) {1523; CHECK-LABEL: f5_3_2:1524; CHECK: # %bb.0: # %entry1525; CHECK-NEXT: #APP1526; CHECK-NEXT: alsi 0(%r2), -11527; CHECK-EMPTY:1528; CHECK-NEXT: #NO_APP1529; CHECK-NEXT: lghi %r2, 51530; CHECK-NEXT: blr %r141531; CHECK-NEXT: .LBB65_1: # %entry1532; CHECK-NEXT: lghi %r2, 151533; CHECK-NEXT: br %r141534entry:1535 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1536 %tmp = icmp ult i32 %cc, 41537 tail call void @llvm.assume(i1 %tmp)1538 %trunc = trunc i32 %cc to i11539 %cmpeq3 = icmp eq i32 %cc, 31540 %cond.inv = xor i1 %cmpeq3, %trunc1541 %res = select i1 %cond.inv, i64 5, i64 151542 ret i64 %res1543}1544 1545; Check branching on 'tm' and 'xor' with one operand cc and the other1546; select_ccmask(cc !=2).1547define i64 @f5_3_3(ptr %a) {1548; CHECK-LABEL: f5_3_3:1549; CHECK: # %bb.0: # %entry1550; CHECK-NEXT: #APP1551; CHECK-NEXT: alsi 0(%r2), -11552; CHECK-EMPTY:1553; CHECK-NEXT: #NO_APP1554; CHECK-NEXT: lghi %r2, 51555; CHECK-NEXT: bhr %r141556; CHECK-NEXT: .LBB66_1: # %entry1557; CHECK-NEXT: lghi %r2, 151558; CHECK-NEXT: br %r141559entry:1560 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1561 %tmp = icmp ult i32 %cc, 41562 tail call void @llvm.assume(i1 %tmp)1563 %trunc = trunc i32 %cc to i11564 %cmpne0 = icmp ne i32 %cc, 01565 %cond.inv = xor i1 %cmpne0, %trunc1566 %res = select i1 %cond.inv, i64 5, i64 151567 ret i64 %res1568}1569 1570; Check 'or' with both operands select_ccmask with TM and ICMP(cc == 1).1571define i64 @f5_4_1(ptr %a) {1572; CHECK-LABEL: f5_4_1:1573; CHECK: # %bb.0: # %entry1574; CHECK-NEXT: #APP1575; CHECK-NEXT: alsi 0(%r2), -11576; CHECK-EMPTY:1577; CHECK-NEXT: #NO_APP1578; CHECK-NEXT: lghi %r2, 51579; CHECK-NEXT: bnlr %r141580; CHECK-NEXT: .LBB67_1: # %entry1581; CHECK-NEXT: lghi %r2, 151582; CHECK-NEXT: br %r141583entry:1584 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1585 %tmp = icmp ult i32 %cc, 41586 tail call void @llvm.assume(i1 %tmp)1587 %andcc = and i32 %cc, 11588 %cmpeq0 = icmp eq i32 %andcc, 01589 %cmpeq3 = icmp eq i32 %cc, 31590 %cond.inv = or i1 %cmpeq3, %cmpeq01591 %res = select i1 %cond.inv, i64 5, i64 151592 ret i64 %res1593}1594 1595; Check 'or' for (cc == 0|1).1596define i64 @f5_4_2(ptr %a) {1597; CHECK-LABEL: f5_4_2:1598; CHECK: # %bb.0: # %entry1599; CHECK-NEXT: #APP1600; CHECK-NEXT: alsi 0(%r2), -11601; CHECK-EMPTY:1602; CHECK-NEXT: #NO_APP1603; CHECK-NEXT: lghi %r2, 51604; CHECK-NEXT: bnler %r141605; CHECK-NEXT: .LBB68_1: # %entry1606; CHECK-NEXT: lghi %r2, 151607; CHECK-NEXT: br %r141608entry:1609 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1610 %tmp = icmp ult i32 %cc, 41611 tail call void @llvm.assume(i1 %tmp)1612 %or = or disjoint i32 %cc, -41613 %cond.inv = icmp samesign ugt i32 %or, -31614 %res = select i1 %cond.inv, i64 5, i64 151615 ret i64 %res1616}1617 1618; Check 'or' for (cc == 0|1).1619define i64 @f5_4_3(ptr %a) {1620; CHECK-LABEL: f5_4_3:1621; CHECK: # %bb.0: # %entry1622; CHECK-NEXT: #APP1623; CHECK-NEXT: alsi 0(%r2), -11624; CHECK-EMPTY:1625; CHECK-NEXT: #NO_APP1626; CHECK-NEXT: lghi %r2, 151627; CHECK-NEXT: bler %r141628; CHECK-NEXT: .LBB69_1: # %entry1629; CHECK-NEXT: lghi %r2, 51630; CHECK-NEXT: br %r141631entry:1632 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1633 %tmp = icmp ult i32 %cc, 41634 tail call void @llvm.assume(i1 %tmp)1635 %or = or disjoint i32 %cc, -41636 %cond = icmp samesign ult i32 %or, -21637 %res = select i1 %cond, i64 15, i64 51638 ret i64 %res1639}1640 1641; Nested select_ccmask with TrueVal and FalseVal swapped with each other.1642define i64 @f6_1(ptr %a) {1643; CHECK-LABEL: f6_1:1644; CHECK: # %bb.0: # %entry1645; CHECK-NEXT: #APP1646; CHECK-NEXT: alsi 0(%r2), -11647; CHECK-EMPTY:1648; CHECK-NEXT: #NO_APP1649; CHECK-NEXT: lghi %r2, 151650; CHECK-NEXT: bher %r141651; CHECK-NEXT: .LBB70_1: # %entry1652; CHECK-NEXT: lghi %r2, 51653; CHECK-NEXT: br %r141654entry:1655 %cc = tail call i32 asm sideeffect "alsi $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr elementtype(i32) %a, ptr elementtype(i32) %a)1656 %cmp = icmp ult i32 %cc, 41657 tail call void @llvm.assume(i1 %cmp)1658 %andcc = and i32 %cc, 11659 %cmpeq0 = icmp eq i32 %andcc, 01660 %cmpeq3 = icmp eq i32 %cc, 31661 %select = select i1 %cmpeq3, i64 5, i64 151662 %res = select i1 %cmpeq0, i64 %select, i64 51663 ret i64 %res1664}1665 1666