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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=s390x-linux-gnu -mcpu=zEC12 < %s | FileCheck %s3;4; Test inline assembly where the operand is bitcasted.5 6define signext i16 @short_and_f(i16 signext %cc_dep1) {7; CHECK-LABEL: short_and_f:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: sllg %r0, %r2, 4810; CHECK-NEXT: ldgr %f1, %r011; CHECK-NEXT: # kill: def $f1h killed $f1h killed $f1d12; CHECK-NEXT: #APP13; CHECK-NEXT: #NO_APP14; CHECK-NEXT: # kill: def $f1h killed $f1h def $f1d15; CHECK-NEXT: lgdr %r0, %f116; CHECK-NEXT: srag %r2, %r0, 4817; CHECK-NEXT: br %r1418entry:19 %0 = tail call i16 asm sideeffect "", "={f1},0"(i16 %cc_dep1)20 ret i16 %021}22 23define signext i32 @int_and_f(i32 signext %cc_dep1) {24; CHECK-LABEL: int_and_f:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: risbhg %r0, %r2, 0, 159, 3227; CHECK-NEXT: ldgr %f1, %r028; CHECK-NEXT: # kill: def $f1s killed $f1s killed $f1d29; CHECK-NEXT: #APP30; CHECK-NEXT: #NO_APP31; CHECK-NEXT: # kill: def $f1s killed $f1s def $f1d32; CHECK-NEXT: lgdr %r0, %f133; CHECK-NEXT: risblg %r0, %r0, 0, 159, 3234; CHECK-NEXT: lgfr %r2, %r035; CHECK-NEXT: br %r1436entry:37 %0 = tail call i32 asm sideeffect "", "={f1},0"(i32 %cc_dep1)38 ret i32 %039}40 41define i64 @long_and_f(i64 %cc_dep1) {42; CHECK-LABEL: long_and_f:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: ldgr %f2, %r245; CHECK-NEXT: #APP46; CHECK-NEXT: #NO_APP47; CHECK-NEXT: lgdr %r2, %f248; CHECK-NEXT: br %r1449entry:50 %0 = tail call i64 asm sideeffect "", "={f2},0"(i64 %cc_dep1)51 ret i64 %052}53 54define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) {55; CHECK-LABEL: __int128_and_f:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: ld %f1, 0(%r3)58; CHECK-NEXT: ld %f3, 8(%r3)59; CHECK-NEXT: #APP60; CHECK-NEXT: #NO_APP61; CHECK-NEXT: std %f1, 0(%r2)62; CHECK-NEXT: std %f3, 8(%r2)63; CHECK-NEXT: br %r1464entry:65 %cc_dep1 = load i128, ptr %0, align 866 %1 = tail call i128 asm sideeffect "", "={f1},0"(i128 %cc_dep1)67 store i128 %1, ptr %agg.result, align 868 ret void69}70 71define half @half_and_r(half %cc_dep1) {72; CHECK-LABEL: half_and_r:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: # kill: def $f0h killed $f0h def $f0d75; CHECK-NEXT: lgdr %r0, %f076; CHECK-NEXT: srlg %r2, %r0, 4877; CHECK-NEXT: #APP78; CHECK-NEXT: #NO_APP79; CHECK-NEXT: sllg %r0, %r2, 4880; CHECK-NEXT: ldgr %f0, %r081; CHECK-NEXT: # kill: def $f0h killed $f0h killed $f0d82; CHECK-NEXT: br %r1483entry:84 %0 = tail call half asm sideeffect "", "={r2},0"(half %cc_dep1)85 ret half %086}87 88define float @float_and_r(float %cc_dep1) {89; CHECK-LABEL: float_and_r:90; CHECK: # %bb.0: # %entry91; CHECK-NEXT: # kill: def $f0s killed $f0s def $f0d92; CHECK-NEXT: lgdr %r0, %f093; CHECK-NEXT: risblg %r2, %r0, 0, 159, 3294; CHECK-NEXT: #APP95; CHECK-NEXT: #NO_APP96; CHECK-NEXT: risbhg %r0, %r2, 0, 159, 3297; CHECK-NEXT: ldgr %f0, %r098; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d99; CHECK-NEXT: br %r14100entry:101 %0 = tail call float asm sideeffect "", "={r2},0"(float %cc_dep1)102 ret float %0103}104 105define double @double_and_r(double %cc_dep1) {106; CHECK-LABEL: double_and_r:107; CHECK: # %bb.0: # %entry108; CHECK-NEXT: lgdr %r3, %f0109; CHECK-NEXT: #APP110; CHECK-NEXT: #NO_APP111; CHECK-NEXT: ldgr %f0, %r3112; CHECK-NEXT: br %r14113entry:114 %0 = tail call double asm sideeffect "", "={r3},0"(double %cc_dep1)115 ret double %0116}117 118define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) {119; CHECK-LABEL: longdouble_and_r:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: lg %r5, 8(%r3)122; CHECK-NEXT: lg %r4, 0(%r3)123; CHECK-NEXT: #APP124; CHECK-NEXT: #NO_APP125; CHECK-NEXT: stg %r5, 8(%r2)126; CHECK-NEXT: stg %r4, 0(%r2)127; CHECK-NEXT: br %r14128entry:129 %cc_dep1 = load fp128, ptr %0, align 8130 %1 = tail call fp128 asm sideeffect "", "={r4},0"(fp128 %cc_dep1)131 store fp128 %1, ptr %agg.result, align 8132 ret void133}134 135define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) {136; CHECK-LABEL: vec32_and_r:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d139; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d140; CHECK-NEXT: risbgn %r3, %r2, 32, 47, 16141; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d142; CHECK-NEXT: #APP143; CHECK-NEXT: #NO_APP144; CHECK-NEXT: srlk %r2, %r3, 16145; CHECK-NEXT: br %r14146entry:147 %0 = tail call <2 x i16> asm sideeffect "", "={r3},0"(<2 x i16> %cc_dep1)148 ret <2 x i16> %0149}150 151define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) {152; CHECK-LABEL: vec64_and_r:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d155; CHECK-NEXT: sllg %r5, %r2, 32156; CHECK-NEXT: lr %r5, %r3157; CHECK-NEXT: #APP158; CHECK-NEXT: #NO_APP159; CHECK-NEXT: lgr %r3, %r5160; CHECK-NEXT: srlg %r2, %r5, 32161; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d162; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d163; CHECK-NEXT: br %r14164entry:165 %0 = tail call <2 x i32> asm sideeffect "", "={r5},0"(<2 x i32> %cc_dep1)166 ret <2 x i32> %0167}168 169define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) {170; CHECK-LABEL: vec32_and_f:171; CHECK: # %bb.0: # %entry172; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d173; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d174; CHECK-NEXT: risbgn %r3, %r2, 32, 47, 16175; CHECK-NEXT: risbhg %r0, %r3, 0, 159, 32176; CHECK-NEXT: ldgr %f3, %r0177; CHECK-NEXT: # kill: def $f3s killed $f3s killed $f3d178; CHECK-NEXT: #APP179; CHECK-NEXT: #NO_APP180; CHECK-NEXT: # kill: def $f3s killed $f3s def $f3d181; CHECK-NEXT: lgdr %r0, %f3182; CHECK-NEXT: risblg %r3, %r0, 0, 159, 32183; CHECK-NEXT: srlk %r2, %r3, 16184; CHECK-NEXT: br %r14185entry:186 %0 = tail call <2 x i16> asm sideeffect "", "={f3},0"(<2 x i16> %cc_dep1)187 ret <2 x i16> %0188}189 190define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) {191; CHECK-LABEL: vec64_and_f:192; CHECK: # %bb.0: # %entry193; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d194; CHECK-NEXT: sllg %r0, %r2, 32195; CHECK-NEXT: lr %r0, %r3196; CHECK-NEXT: ldgr %f4, %r0197; CHECK-NEXT: #APP198; CHECK-NEXT: #NO_APP199; CHECK-NEXT: lgdr %r3, %f4200; CHECK-NEXT: srlg %r2, %r3, 32201; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d202; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d203; CHECK-NEXT: br %r14204entry:205 %0 = tail call <2 x i32> asm sideeffect "", "={f4},0"(<2 x i32> %cc_dep1)206 ret <2 x i32> %0207}208 209define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) {210; CHECK-LABEL: vec128_and_f:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: aghi %r15, -176213; CHECK-NEXT: .cfi_def_cfa_offset 336214; CHECK-NEXT: # kill: def $r4l killed $r4l def $r4d215; CHECK-NEXT: sllg %r0, %r4, 32216; CHECK-NEXT: lr %r0, %r5217; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d218; CHECK-NEXT: stg %r0, 168(%r15)219; CHECK-NEXT: sllg %r0, %r2, 32220; CHECK-NEXT: lr %r0, %r3221; CHECK-NEXT: stg %r0, 160(%r15)222; CHECK-NEXT: ld %f0, 160(%r15)223; CHECK-NEXT: ld %f2, 168(%r15)224; CHECK-NEXT: #APP225; CHECK-NEXT: #NO_APP226; CHECK-NEXT: lgdr %r3, %f0227; CHECK-NEXT: lgdr %r5, %f2228; CHECK-NEXT: srlg %r2, %r3, 32229; CHECK-NEXT: srlg %r4, %r5, 32230; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d231; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d232; CHECK-NEXT: # kill: def $r4l killed $r4l killed $r4d233; CHECK-NEXT: # kill: def $r5l killed $r5l killed $r5d234; CHECK-NEXT: aghi %r15, 176235; CHECK-NEXT: br %r14236entry:237 %0 = tail call <4 x i32> asm sideeffect "", "={f0},0"(<4 x i32> %cc_dep1)238 ret <4 x i32> %0239}240 241