314 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 < %s | FileCheck %s --check-prefixes=CHECK,Z153; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s --check-prefixes=CHECK,Z134;5; Test inline assembly where the operand is bitcasted.6 7define signext i16 @short_and_f(i16 signext %cc_dep1) {8; CHECK-LABEL: short_and_f:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vlvgh %v0, %r2, 011; CHECK-NEXT: #APP12; CHECK-NEXT: #NO_APP13; CHECK-NEXT: vlgvh %r0, %v0, 014; CHECK-NEXT: lghr %r2, %r015; CHECK-NEXT: br %r1416entry:17 %0 = tail call i16 asm sideeffect "", "={f0},0"(i16 %cc_dep1)18 ret i16 %019}20 21define signext i32 @int_and_f(i32 signext %cc_dep1) {22; CHECK-LABEL: int_and_f:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vlvgf %v0, %r2, 025; CHECK-NEXT: #APP26; CHECK-NEXT: #NO_APP27; CHECK-NEXT: vlgvf %r0, %v0, 028; CHECK-NEXT: lgfr %r2, %r029; CHECK-NEXT: br %r1430entry:31 %0 = tail call i32 asm sideeffect "", "={f0},0"(i32 %cc_dep1)32 ret i32 %033}34 35define i64 @long_and_f(i64 %cc_dep1) {36; CHECK-LABEL: long_and_f:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: ldgr %f1, %r239; CHECK-NEXT: #APP40; CHECK-NEXT: #NO_APP41; CHECK-NEXT: lgdr %r2, %f142; CHECK-NEXT: br %r1443entry:44 %0 = tail call i64 asm sideeffect "", "={f1},0"(i64 %cc_dep1)45 ret i64 %046}47 48define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) {49; Z15-LABEL: __int128_and_f:50; Z15: # %bb.0: # %entry51; Z15-NEXT: vl %v0, 0(%r3), 352; Z15-NEXT: vlr %v4, %v053; Z15-NEXT: vrepg %v6, %v0, 154; Z15-NEXT: #APP55; Z15-NEXT: #NO_APP56; Z15-NEXT: vmrhg %v0, %v4, %v657; Z15-NEXT: vst %v0, 0(%r2), 358; Z15-NEXT: br %r1459;60; Z13-LABEL: __int128_and_f:61; Z13: # %bb.0: # %entry62; Z13-NEXT: ld %f4, 0(%r3)63; Z13-NEXT: ld %f6, 8(%r3)64; Z13-NEXT: #APP65; Z13-NEXT: #NO_APP66; Z13-NEXT: std %f4, 0(%r2)67; Z13-NEXT: std %f6, 8(%r2)68; Z13-NEXT: br %r1469entry:70 %cc_dep1 = load i128, ptr %0, align 871 %1 = tail call i128 asm sideeffect "", "={f4},0"(i128 %cc_dep1)72 store i128 %1, ptr %agg.result, align 873 ret void74}75 76define signext i32 @int_and_v(i32 signext %cc_dep1) {77; CHECK-LABEL: int_and_v:78; CHECK: # %bb.0: # %entry79; CHECK-NEXT: vlvgf %v0, %r2, 080; CHECK-NEXT: #APP81; CHECK-NEXT: #NO_APP82; CHECK-NEXT: vlgvf %r0, %v0, 083; CHECK-NEXT: lgfr %r2, %r084; CHECK-NEXT: br %r1485entry:86 %0 = tail call i32 asm sideeffect "", "={v0},0"(i32 %cc_dep1)87 ret i32 %088}89 90define i64 @long_and_v(i64 %cc_dep1) {91; CHECK-LABEL: long_and_v:92; CHECK: # %bb.0: # %entry93; CHECK-NEXT: ldgr %f1, %r294; CHECK-NEXT: #APP95; CHECK-NEXT: #NO_APP96; CHECK-NEXT: lgdr %r2, %f197; CHECK-NEXT: br %r1498entry:99 %0 = tail call i64 asm sideeffect "", "={v1},0"(i64 %cc_dep1)100 ret i64 %0101}102 103define void @__int128_and_v(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) {104; CHECK-LABEL: __int128_and_v:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vl %v2, 0(%r3), 3107; CHECK-NEXT: #APP108; CHECK-NEXT: #NO_APP109; CHECK-NEXT: vst %v2, 0(%r2), 3110; CHECK-NEXT: br %r14111entry:112 %cc_dep1 = load i128, ptr %0, align 8113 %1 = tail call i128 asm sideeffect "", "={v2},0"(i128 %cc_dep1)114 store i128 %1, ptr %agg.result, align 8115 ret void116}117 118define half @half_and_r(half %cc_dep1) {119; CHECK-LABEL: half_and_r:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: vlgvh %r0, %v0, 0122; CHECK-NEXT: #APP123; CHECK-NEXT: #NO_APP124; CHECK-NEXT: vlvgh %v0, %r0, 0125; CHECK-NEXT: br %r14126entry:127 %0 = tail call half asm sideeffect "", "={r0},0"(half %cc_dep1)128 ret half %0129}130 131define float @float_and_r(float %cc_dep1) {132; CHECK-LABEL: float_and_r:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vlgvf %r0, %v0, 0135; CHECK-NEXT: # kill: def $r0l killed $r0l killed $r0d136; CHECK-NEXT: #APP137; CHECK-NEXT: #NO_APP138; CHECK-NEXT: vlvgf %v0, %r0, 0139; CHECK-NEXT: br %r14140entry:141 %0 = tail call float asm sideeffect "", "={r0},0"(float %cc_dep1)142 ret float %0143}144 145define double @double_and_r(double %cc_dep1) {146; CHECK-LABEL: double_and_r:147; CHECK: # %bb.0: # %entry148; CHECK-NEXT: lgdr %r1, %f0149; CHECK-NEXT: #APP150; CHECK-NEXT: #NO_APP151; CHECK-NEXT: ldgr %f0, %r1152; CHECK-NEXT: br %r14153entry:154 %0 = tail call double asm sideeffect "", "={r1},0"(double %cc_dep1)155 ret double %0156}157 158define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) {159; CHECK-LABEL: longdouble_and_r:160; CHECK: # %bb.0: # %entry161; CHECK-NEXT: lg %r5, 8(%r3)162; CHECK-NEXT: lg %r4, 0(%r3)163; CHECK-NEXT: #APP164; CHECK-NEXT: #NO_APP165; CHECK-NEXT: stg %r5, 8(%r2)166; CHECK-NEXT: stg %r4, 0(%r2)167; CHECK-NEXT: br %r14168entry:169 %cc_dep1 = load fp128, ptr %0, align 8170 %1 = tail call fp128 asm sideeffect "", "={r4},0"(fp128 %cc_dep1)171 store fp128 %1, ptr %agg.result, align 8172 ret void173}174 175define half @half_and_v(half %cc_dep1) {176; CHECK-LABEL: half_and_v:177; CHECK: # %bb.0: # %entry178; CHECK-NEXT: ldr %f3, %f0179; CHECK-NEXT: #APP180; CHECK-NEXT: #NO_APP181; CHECK-NEXT: ldr %f0, %f3182; CHECK-NEXT: br %r14183entry:184 %0 = tail call half asm sideeffect "", "={v3},0"(half %cc_dep1)185 ret half %0186}187 188define float @float_and_v(float %cc_dep1) {189; CHECK-LABEL: float_and_v:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: ldr %f3, %f0192; CHECK-NEXT: #APP193; CHECK-NEXT: #NO_APP194; CHECK-NEXT: ldr %f0, %f3195; CHECK-NEXT: br %r14196entry:197 %0 = tail call float asm sideeffect "", "={v3},0"(float %cc_dep1)198 ret float %0199}200 201define double @double_and_v(double %cc_dep1) {202; CHECK-LABEL: double_and_v:203; CHECK: # %bb.0: # %entry204; CHECK-NEXT: ldr %f4, %f0205; CHECK-NEXT: #APP206; CHECK-NEXT: #NO_APP207; CHECK-NEXT: ldr %f0, %f4208; CHECK-NEXT: br %r14209entry:210 %0 = tail call double asm sideeffect "", "={v4},0"(double %cc_dep1)211 ret double %0212}213 214define void @longdouble_and_v(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) {215; CHECK-LABEL: longdouble_and_v:216; CHECK: # %bb.0: # %entry217; CHECK-NEXT: vl %v5, 0(%r3), 3218; CHECK-NEXT: #APP219; CHECK-NEXT: #NO_APP220; CHECK-NEXT: vst %v5, 0(%r2), 3221; CHECK-NEXT: br %r14222entry:223 %cc_dep1 = load fp128, ptr %0, align 8224 %1 = tail call fp128 asm sideeffect "", "={v5},0"(fp128 %cc_dep1)225 store fp128 %1, ptr %agg.result, align 8226 ret void227}228 229define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) {230; CHECK-LABEL: vec32_and_r:231; CHECK: # %bb.0: # %entry232; CHECK-NEXT: vlgvf %r5, %v24, 0233; CHECK-NEXT: # kill: def $r5l killed $r5l killed $r5d234; CHECK-NEXT: #APP235; CHECK-NEXT: #NO_APP236; CHECK-NEXT: vlvgf %v24, %r5, 0237; CHECK-NEXT: br %r14238entry:239 %0 = tail call <2 x i16> asm sideeffect "", "={r5},0"(<2 x i16> %cc_dep1)240 ret <2 x i16> %0241}242 243define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) {244; CHECK-LABEL: vec64_and_r:245; CHECK: # %bb.0: # %entry246; CHECK-NEXT: vlgvg %r4, %v24, 0247; CHECK-NEXT: #APP248; CHECK-NEXT: #NO_APP249; CHECK-NEXT: vlvgg %v24, %r4, 0250; CHECK-NEXT: br %r14251entry:252 %0 = tail call <2 x i32> asm sideeffect "", "={r4},0"(<2 x i32> %cc_dep1)253 ret <2 x i32> %0254}255 256define <4 x i32> @vec128_and_r(<4 x i32> %cc_dep1) {257; CHECK-LABEL: vec128_and_r:258; CHECK: # %bb.0: # %entry259; CHECK-NEXT: vlgvg %r3, %v24, 1260; CHECK-NEXT: vlgvg %r2, %v24, 0261; CHECK-NEXT: #APP262; CHECK-NEXT: #NO_APP263; CHECK-NEXT: vlvgp %v24, %r2, %r3264; CHECK-NEXT: br %r14265entry:266 %0 = tail call <4 x i32> asm sideeffect "", "={r2},0"(<4 x i32> %cc_dep1)267 ret <4 x i32> %0268}269 270define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) {271; CHECK-LABEL: vec32_and_f:272; CHECK: # %bb.0: # %entry273; CHECK-NEXT: vlr %v4, %v24274; CHECK-NEXT: # kill: def $f4s killed $f4s killed $v4275; CHECK-NEXT: #APP276; CHECK-NEXT: #NO_APP277; CHECK-NEXT: # kill: def $f4s killed $f4s def $v4278; CHECK-NEXT: vlr %v24, %v4279; CHECK-NEXT: br %r14280entry:281 %0 = tail call <2 x i16> asm sideeffect "", "={f4},0"(<2 x i16> %cc_dep1)282 ret <2 x i16> %0283}284 285define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) {286; CHECK-LABEL: vec64_and_f:287; CHECK: # %bb.0: # %entry288; CHECK-NEXT: vlr %v5, %v24289; CHECK-NEXT: # kill: def $f5d killed $f5d killed $v5290; CHECK-NEXT: #APP291; CHECK-NEXT: #NO_APP292; CHECK-NEXT: # kill: def $f5d killed $f5d def $v5293; CHECK-NEXT: vlr %v24, %v5294; CHECK-NEXT: br %r14295entry:296 %0 = tail call <2 x i32> asm sideeffect "", "={f5},0"(<2 x i32> %cc_dep1)297 ret <2 x i32> %0298}299 300define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) {301; CHECK-LABEL: vec128_and_f:302; CHECK: # %bb.0: # %entry303; CHECK-NEXT: vlr %v1, %v24304; CHECK-NEXT: vrepg %v3, %v24, 1305; CHECK-NEXT: #APP306; CHECK-NEXT: #NO_APP307; CHECK-NEXT: vmrhg %v24, %v1, %v3308; CHECK-NEXT: br %r14309entry:310 %0 = tail call <4 x i32> asm sideeffect "", "={f1},0"(<4 x i32> %cc_dep1)311 ret <4 x i32> %0312}313 314