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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=s390x-linux-gnu -mcpu=zEC12 < %s | FileCheck %s3;4; Test inline assembly where the operand is bitcasted.5 6define signext i16 @short_and_f(i16 signext %cc_dep1) {7; CHECK-LABEL: short_and_f:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: sllg %r0, %r2, 4810; CHECK-NEXT: ldgr %f0, %r011; CHECK-NEXT: #APP12; CHECK-NEXT: #NO_APP13; CHECK-NEXT: lgdr %r0, %f014; CHECK-NEXT: srag %r2, %r0, 4815; CHECK-NEXT: br %r1416entry:17 %0 = tail call i16 asm sideeffect "", "=f,0"(i16 %cc_dep1)18 ret i16 %019}20 21define signext i32 @int_and_f(i32 signext %cc_dep1) {22; CHECK-LABEL: int_and_f:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: risbhg %r0, %r2, 0, 159, 3225; CHECK-NEXT: ldgr %f0, %r026; CHECK-NEXT: #APP27; CHECK-NEXT: #NO_APP28; CHECK-NEXT: lgdr %r0, %f029; CHECK-NEXT: risblg %r0, %r0, 0, 159, 3230; CHECK-NEXT: lgfr %r2, %r031; CHECK-NEXT: br %r1432entry:33 %0 = tail call i32 asm sideeffect "", "=f,0"(i32 %cc_dep1)34 ret i32 %035}36 37define i64 @long_and_f(i64 %cc_dep1) {38; CHECK-LABEL: long_and_f:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: ldgr %f0, %r241; CHECK-NEXT: #APP42; CHECK-NEXT: #NO_APP43; CHECK-NEXT: lgdr %r2, %f044; CHECK-NEXT: br %r1445entry:46 %0 = tail call i64 asm sideeffect "", "=f,0"(i64 %cc_dep1)47 ret i64 %048}49 50define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) {51; CHECK-LABEL: __int128_and_f:52; CHECK: # %bb.0: # %entry53; CHECK-NEXT: ld %f0, 0(%r3)54; CHECK-NEXT: ld %f2, 8(%r3)55; CHECK-NEXT: #APP56; CHECK-NEXT: #NO_APP57; CHECK-NEXT: std %f0, 0(%r2)58; CHECK-NEXT: std %f2, 8(%r2)59; CHECK-NEXT: br %r1460entry:61 %cc_dep1 = load i128, ptr %0, align 862 %1 = tail call i128 asm sideeffect "", "=f,0"(i128 %cc_dep1)63 store i128 %1, ptr %agg.result, align 864 ret void65}66 67define half @half_and_r(half %cc_dep1) {68; CHECK-LABEL: half_and_r:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: # kill: def $f0h killed $f0h def $f0d71; CHECK-NEXT: lgdr %r0, %f072; CHECK-NEXT: srlg %r0, %r0, 4873; CHECK-NEXT: #APP74; CHECK-NEXT: #NO_APP75; CHECK-NEXT: sllg %r0, %r0, 4876; CHECK-NEXT: ldgr %f0, %r077; CHECK-NEXT: # kill: def $f0h killed $f0h killed $f0d78; CHECK-NEXT: br %r1479entry:80 %0 = tail call half asm sideeffect "", "=r,0"(half %cc_dep1)81 ret half %082}83 84define float @float_and_r(float %cc_dep1) {85; CHECK-LABEL: float_and_r:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: # kill: def $f0s killed $f0s def $f0d88; CHECK-NEXT: lgdr %r0, %f089; CHECK-NEXT: risblg %r0, %r0, 0, 159, 3290; CHECK-NEXT: #APP91; CHECK-NEXT: #NO_APP92; CHECK-NEXT: risbhg %r0, %r0, 0, 159, 3293; CHECK-NEXT: ldgr %f0, %r094; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d95; CHECK-NEXT: br %r1496entry:97 %0 = tail call float asm sideeffect "", "=r,0"(float %cc_dep1)98 ret float %099}100 101define double @double_and_r(double %cc_dep1) {102; CHECK-LABEL: double_and_r:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: lgdr %r0, %f0105; CHECK-NEXT: #APP106; CHECK-NEXT: #NO_APP107; CHECK-NEXT: ldgr %f0, %r0108; CHECK-NEXT: br %r14109entry:110 %0 = tail call double asm sideeffect "", "=r,0"(double %cc_dep1)111 ret double %0112}113 114define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) {115; CHECK-LABEL: longdouble_and_r:116; CHECK: # %bb.0: # %entry117; CHECK-NEXT: lg %r1, 8(%r3)118; CHECK-NEXT: lg %r0, 0(%r3)119; CHECK-NEXT: #APP120; CHECK-NEXT: #NO_APP121; CHECK-NEXT: stg %r1, 8(%r2)122; CHECK-NEXT: stg %r0, 0(%r2)123; CHECK-NEXT: br %r14124entry:125 %cc_dep1 = load fp128, ptr %0, align 8126 %1 = tail call fp128 asm sideeffect "", "=r,0"(fp128 %cc_dep1)127 store fp128 %1, ptr %agg.result, align 8128 ret void129}130 131define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) {132; CHECK-LABEL: vec32_and_r:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d135; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d136; CHECK-NEXT: risbgn %r3, %r2, 32, 47, 16137; CHECK-NEXT: #APP138; CHECK-NEXT: #NO_APP139; CHECK-NEXT: srlk %r2, %r3, 16140; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d141; CHECK-NEXT: br %r14142entry:143 %0 = tail call <2 x i16> asm sideeffect "", "=r,0"(<2 x i16> %cc_dep1)144 ret <2 x i16> %0145}146 147define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) {148; CHECK-LABEL: vec64_and_r:149; CHECK: # %bb.0: # %entry150; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d151; CHECK-NEXT: sllg %r0, %r2, 32152; CHECK-NEXT: lr %r0, %r3153; CHECK-NEXT: #APP154; CHECK-NEXT: #NO_APP155; CHECK-NEXT: lr %r3, %r0156; CHECK-NEXT: srlg %r2, %r0, 32157; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d158; CHECK-NEXT: br %r14159entry:160 %0 = tail call <2 x i32> asm sideeffect "", "=r,0"(<2 x i32> %cc_dep1)161 ret <2 x i32> %0162}163 164define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) {165; CHECK-LABEL: vec32_and_f:166; CHECK: # %bb.0: # %entry167; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d168; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d169; CHECK-NEXT: risbgn %r3, %r2, 32, 47, 16170; CHECK-NEXT: risbhg %r0, %r3, 0, 159, 32171; CHECK-NEXT: ldgr %f0, %r0172; CHECK-NEXT: #APP173; CHECK-NEXT: #NO_APP174; CHECK-NEXT: lgdr %r0, %f0175; CHECK-NEXT: risblg %r3, %r0, 0, 159, 32176; CHECK-NEXT: srlk %r2, %r3, 16177; CHECK-NEXT: br %r14178entry:179 %0 = tail call <2 x i16> asm sideeffect "", "=f,0"(<2 x i16> %cc_dep1)180 ret <2 x i16> %0181}182 183define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) {184; CHECK-LABEL: vec64_and_f:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d187; CHECK-NEXT: sllg %r0, %r2, 32188; CHECK-NEXT: lr %r0, %r3189; CHECK-NEXT: ldgr %f0, %r0190; CHECK-NEXT: #APP191; CHECK-NEXT: #NO_APP192; CHECK-NEXT: lgdr %r3, %f0193; CHECK-NEXT: srlg %r2, %r3, 32194; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d195; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d196; CHECK-NEXT: br %r14197entry:198 %0 = tail call <2 x i32> asm sideeffect "", "=f,0"(<2 x i32> %cc_dep1)199 ret <2 x i32> %0200}201 202define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) {203; CHECK-LABEL: vec128_and_f:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: aghi %r15, -176206; CHECK-NEXT: .cfi_def_cfa_offset 336207; CHECK-NEXT: # kill: def $r4l killed $r4l def $r4d208; CHECK-NEXT: sllg %r0, %r4, 32209; CHECK-NEXT: lr %r0, %r5210; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d211; CHECK-NEXT: stg %r0, 168(%r15)212; CHECK-NEXT: sllg %r0, %r2, 32213; CHECK-NEXT: lr %r0, %r3214; CHECK-NEXT: stg %r0, 160(%r15)215; CHECK-NEXT: ld %f0, 160(%r15)216; CHECK-NEXT: ld %f2, 168(%r15)217; CHECK-NEXT: #APP218; CHECK-NEXT: #NO_APP219; CHECK-NEXT: lgdr %r3, %f0220; CHECK-NEXT: lgdr %r5, %f2221; CHECK-NEXT: srlg %r2, %r3, 32222; CHECK-NEXT: srlg %r4, %r5, 32223; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d224; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d225; CHECK-NEXT: # kill: def $r4l killed $r4l killed $r4d226; CHECK-NEXT: # kill: def $r5l killed $r5l killed $r5d227; CHECK-NEXT: aghi %r15, 176228; CHECK-NEXT: br %r14229entry:230 %0 = tail call <4 x i32> asm sideeffect "", "=f,0"(<4 x i32> %cc_dep1)231 ret <4 x i32> %0232}233 234