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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 < %s | FileCheck %s --check-prefixes=CHECK,Z153; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s --check-prefixes=CHECK,Z134;5; Test inline assembly where the operand is bitcasted.6 7define signext i16 @short_and_f(i16 signext %cc_dep1) {8; CHECK-LABEL: short_and_f:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vlvgh %v0, %r2, 011; CHECK-NEXT: #APP12; CHECK-NEXT: #NO_APP13; CHECK-NEXT: vlgvh %r0, %v0, 014; CHECK-NEXT: lghr %r2, %r015; CHECK-NEXT: br %r1416entry:17 %0 = tail call i16 asm sideeffect "", "=f,0"(i16 %cc_dep1)18 ret i16 %019}20 21define signext i32 @int_and_f(i32 signext %cc_dep1) {22; CHECK-LABEL: int_and_f:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vlvgf %v0, %r2, 025; CHECK-NEXT: #APP26; CHECK-NEXT: #NO_APP27; CHECK-NEXT: vlgvf %r0, %v0, 028; CHECK-NEXT: lgfr %r2, %r029; CHECK-NEXT: br %r1430entry:31 %0 = tail call i32 asm sideeffect "", "=f,0"(i32 %cc_dep1)32 ret i32 %033}34 35define i64 @long_and_f(i64 %cc_dep1) {36; CHECK-LABEL: long_and_f:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: ldgr %f0, %r239; CHECK-NEXT: #APP40; CHECK-NEXT: #NO_APP41; CHECK-NEXT: lgdr %r2, %f042; CHECK-NEXT: br %r1443entry:44 %0 = tail call i64 asm sideeffect "", "=f,0"(i64 %cc_dep1)45 ret i64 %046}47 48define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) {49; Z15-LABEL: __int128_and_f:50; Z15: # %bb.0: # %entry51; Z15-NEXT: vl %v0, 0(%r3), 352; Z15-NEXT: vrepg %v2, %v0, 153; Z15-NEXT: #APP54; Z15-NEXT: #NO_APP55; Z15-NEXT: vmrhg %v0, %v0, %v256; Z15-NEXT: vst %v0, 0(%r2), 357; Z15-NEXT: br %r1458;59; Z13-LABEL: __int128_and_f:60; Z13: # %bb.0: # %entry61; Z13-NEXT: ld %f0, 0(%r3)62; Z13-NEXT: ld %f2, 8(%r3)63; Z13-NEXT: #APP64; Z13-NEXT: #NO_APP65; Z13-NEXT: std %f0, 0(%r2)66; Z13-NEXT: std %f2, 8(%r2)67; Z13-NEXT: br %r1468entry:69 %cc_dep1 = load i128, ptr %0, align 870 %1 = tail call i128 asm sideeffect "", "=f,0"(i128 %cc_dep1)71 store i128 %1, ptr %agg.result, align 872 ret void73}74 75define signext i16 @short_and_v(i16 signext %cc_dep1) {76; CHECK-LABEL: short_and_v:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vlvgh %v0, %r2, 079; CHECK-NEXT: #APP80; CHECK-NEXT: #NO_APP81; CHECK-NEXT: vlgvh %r0, %v0, 082; CHECK-NEXT: lghr %r2, %r083; CHECK-NEXT: br %r1484entry:85 %0 = tail call i16 asm sideeffect "", "=v,0"(i16 %cc_dep1)86 ret i16 %087}88 89define signext i32 @int_and_v(i32 signext %cc_dep1) {90; CHECK-LABEL: int_and_v:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vlvgf %v0, %r2, 093; CHECK-NEXT: #APP94; CHECK-NEXT: #NO_APP95; CHECK-NEXT: vlgvf %r0, %v0, 096; CHECK-NEXT: lgfr %r2, %r097; CHECK-NEXT: br %r1498entry:99 %0 = tail call i32 asm sideeffect "", "=v,0"(i32 %cc_dep1)100 ret i32 %0101}102 103define i64 @long_and_v(i64 %cc_dep1) {104; CHECK-LABEL: long_and_v:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: ldgr %f0, %r2107; CHECK-NEXT: #APP108; CHECK-NEXT: #NO_APP109; CHECK-NEXT: lgdr %r2, %f0110; CHECK-NEXT: br %r14111entry:112 %0 = tail call i64 asm sideeffect "", "=v,0"(i64 %cc_dep1)113 ret i64 %0114}115 116define void @__int128_and_v(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) {117; CHECK-LABEL: __int128_and_v:118; CHECK: # %bb.0: # %entry119; CHECK-NEXT: vl %v0, 0(%r3), 3120; CHECK-NEXT: #APP121; CHECK-NEXT: #NO_APP122; CHECK-NEXT: vst %v0, 0(%r2), 3123; CHECK-NEXT: br %r14124entry:125 %cc_dep1 = load i128, ptr %0, align 8126 %1 = tail call i128 asm sideeffect "", "=v,0"(i128 %cc_dep1)127 store i128 %1, ptr %agg.result, align 8128 ret void129}130 131define half @half_and_r(half %cc_dep1) {132; CHECK-LABEL: half_and_r:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vlgvh %r0, %v0, 0135; CHECK-NEXT: #APP136; CHECK-NEXT: #NO_APP137; CHECK-NEXT: vlvgh %v0, %r0, 0138; CHECK-NEXT: br %r14139entry:140 %0 = tail call half asm sideeffect "", "=r,0"(half %cc_dep1)141 ret half %0142}143 144define float @float_and_r(float %cc_dep1) {145; CHECK-LABEL: float_and_r:146; CHECK: # %bb.0: # %entry147; CHECK-NEXT: vlgvf %r0, %v0, 0148; CHECK-NEXT: #APP149; CHECK-NEXT: #NO_APP150; CHECK-NEXT: vlvgf %v0, %r0, 0151; CHECK-NEXT: br %r14152entry:153 %0 = tail call float asm sideeffect "", "=r,0"(float %cc_dep1)154 ret float %0155}156 157define double @double_and_r(double %cc_dep1) {158; CHECK-LABEL: double_and_r:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: lgdr %r0, %f0161; CHECK-NEXT: #APP162; CHECK-NEXT: #NO_APP163; CHECK-NEXT: ldgr %f0, %r0164; CHECK-NEXT: br %r14165entry:166 %0 = tail call double asm sideeffect "", "=r,0"(double %cc_dep1)167 ret double %0168}169 170define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) {171; CHECK-LABEL: longdouble_and_r:172; CHECK: # %bb.0: # %entry173; CHECK-NEXT: lg %r1, 8(%r3)174; CHECK-NEXT: lg %r0, 0(%r3)175; CHECK-NEXT: #APP176; CHECK-NEXT: #NO_APP177; CHECK-NEXT: stg %r1, 8(%r2)178; CHECK-NEXT: stg %r0, 0(%r2)179; CHECK-NEXT: br %r14180entry:181 %cc_dep1 = load fp128, ptr %0, align 8182 %1 = tail call fp128 asm sideeffect "", "=r,0"(fp128 %cc_dep1)183 store fp128 %1, ptr %agg.result, align 8184 ret void185}186 187define half @half_and_v(half %cc_dep1) {188; CHECK-LABEL: half_and_v:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: #APP191; CHECK-NEXT: #NO_APP192; CHECK-NEXT: br %r14193entry:194 %0 = tail call half asm sideeffect "", "=v,0"(half %cc_dep1)195 ret half %0196}197 198define float @float_and_v(float %cc_dep1) {199; CHECK-LABEL: float_and_v:200; CHECK: # %bb.0: # %entry201; CHECK-NEXT: #APP202; CHECK-NEXT: #NO_APP203; CHECK-NEXT: br %r14204entry:205 %0 = tail call float asm sideeffect "", "=v,0"(float %cc_dep1)206 ret float %0207}208 209define double @double_and_v(double %cc_dep1) {210; CHECK-LABEL: double_and_v:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: #APP213; CHECK-NEXT: #NO_APP214; CHECK-NEXT: br %r14215entry:216 %0 = tail call double asm sideeffect "", "=v,0"(double %cc_dep1)217 ret double %0218}219 220define void @longdouble_and_v(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) {221; CHECK-LABEL: longdouble_and_v:222; CHECK: # %bb.0: # %entry223; CHECK-NEXT: vl %v0, 0(%r3), 3224; CHECK-NEXT: #APP225; CHECK-NEXT: #NO_APP226; CHECK-NEXT: vst %v0, 0(%r2), 3227; CHECK-NEXT: br %r14228entry:229 %cc_dep1 = load fp128, ptr %0, align 8230 %1 = tail call fp128 asm sideeffect "", "=v,0"(fp128 %cc_dep1)231 store fp128 %1, ptr %agg.result, align 8232 ret void233}234 235define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) {236; CHECK-LABEL: vec32_and_r:237; CHECK: # %bb.0: # %entry238; CHECK-NEXT: vlgvf %r0, %v24, 0239; CHECK-NEXT: #APP240; CHECK-NEXT: #NO_APP241; CHECK-NEXT: vlvgf %v24, %r0, 0242; CHECK-NEXT: br %r14243entry:244 %0 = tail call <2 x i16> asm sideeffect "", "=r,0"(<2 x i16> %cc_dep1)245 ret <2 x i16> %0246}247 248define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) {249; CHECK-LABEL: vec64_and_r:250; CHECK: # %bb.0: # %entry251; CHECK-NEXT: vlgvg %r0, %v24, 0252; CHECK-NEXT: #APP253; CHECK-NEXT: #NO_APP254; CHECK-NEXT: vlvgg %v24, %r0, 0255; CHECK-NEXT: br %r14256entry:257 %0 = tail call <2 x i32> asm sideeffect "", "=r,0"(<2 x i32> %cc_dep1)258 ret <2 x i32> %0259}260 261define <4 x i32> @vec128_and_r(<4 x i32> %cc_dep1) {262; CHECK-LABEL: vec128_and_r:263; CHECK: # %bb.0: # %entry264; CHECK-NEXT: vlgvg %r1, %v24, 1265; CHECK-NEXT: vlgvg %r0, %v24, 0266; CHECK-NEXT: #APP267; CHECK-NEXT: #NO_APP268; CHECK-NEXT: vlvgp %v24, %r0, %r1269; CHECK-NEXT: br %r14270entry:271 %0 = tail call <4 x i32> asm sideeffect "", "=r,0"(<4 x i32> %cc_dep1)272 ret <4 x i32> %0273}274 275define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) {276; CHECK-LABEL: vec32_and_f:277; CHECK: # %bb.0: # %entry278; CHECK-NEXT: vlr %v0, %v24279; CHECK-NEXT: #APP280; CHECK-NEXT: #NO_APP281; CHECK-NEXT: vlr %v24, %v0282; CHECK-NEXT: br %r14283entry:284 %0 = tail call <2 x i16> asm sideeffect "", "=f,0"(<2 x i16> %cc_dep1)285 ret <2 x i16> %0286}287 288define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) {289; CHECK-LABEL: vec64_and_f:290; CHECK: # %bb.0: # %entry291; CHECK-NEXT: vlr %v0, %v24292; CHECK-NEXT: #APP293; CHECK-NEXT: #NO_APP294; CHECK-NEXT: vlr %v24, %v0295; CHECK-NEXT: br %r14296entry:297 %0 = tail call <2 x i32> asm sideeffect "", "=f,0"(<2 x i32> %cc_dep1)298 ret <2 x i32> %0299}300 301define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) {302; CHECK-LABEL: vec128_and_f:303; CHECK: # %bb.0: # %entry304; CHECK-NEXT: vlr %v0, %v24305; CHECK-NEXT: vrepg %v2, %v24, 1306; CHECK-NEXT: #APP307; CHECK-NEXT: #NO_APP308; CHECK-NEXT: vmrhg %v24, %v0, %v2309; CHECK-NEXT: br %r14310entry:311 %0 = tail call <4 x i32> asm sideeffect "", "=f,0"(<4 x i32> %cc_dep1)312 ret <4 x i32> %0313}314 315