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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=s390x-linux-gnu -no-integrated-as < %s | FileCheck %s3;4 5; Test i128 (tied) operands.6 7define i32 @fun0(ptr %p1, i32 signext %l1, ptr %p2, i32 signext %l2, i8 zeroext %pad) {8; CHECK-LABEL: fun0:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: lgr %r0, %r511; CHECK-NEXT: # kill: def $r4d killed $r4d def $r4q12; CHECK-NEXT: lgr %r1, %r313; CHECK-NEXT: # kill: def $r2d killed $r2d def $r2q14; CHECK-NEXT: sllg %r5, %r6, 2415; CHECK-NEXT: rosbg %r5, %r0, 40, 63, 016; CHECK-NEXT: risbg %r3, %r1, 40, 191, 017; CHECK-NEXT: #APP18; CHECK-NEXT: clcl %r2, %r419; CHECK-NEXT: #NO_APP20; CHECK-NEXT: ogr %r3, %r521; CHECK-NEXT: risbg %r0, %r3, 40, 191, 022; CHECK-NEXT: ipm %r223; CHECK-NEXT: afi %r2, -26843545624; CHECK-NEXT: srl %r2, 3125; CHECK-NEXT: br %r1426entry:27 %0 = ptrtoint ptr %p1 to i6428 %1 = ptrtoint ptr %p2 to i6429 %and5 = and i32 %l2, 1677721530 %2 = zext i32 %and5 to i6431 %conv7 = zext i8 %pad to i6432 %shl = shl nuw nsw i64 %conv7, 2433 %or = or i64 %shl, %234 %u1.sroa.0.0.insert.ext = zext i64 %0 to i12835 %u1.sroa.0.0.insert.shift = shl nuw i128 %u1.sroa.0.0.insert.ext, 6436 %3 = and i32 %l1, 1677721537 %u1.sroa.0.0.insert.mask = zext i32 %3 to i12838 %u1.sroa.0.0.insert.insert = or i128 %u1.sroa.0.0.insert.shift, %u1.sroa.0.0.insert.mask39 %u2.sroa.5.0.insert.ext = zext i64 %or to i12840 %u2.sroa.0.0.insert.ext = zext i64 %1 to i12841 %u2.sroa.0.0.insert.shift = shl nuw i128 %u2.sroa.0.0.insert.ext, 6442 %u2.sroa.0.0.insert.insert = or i128 %u2.sroa.0.0.insert.shift, %u2.sroa.5.0.insert.ext43 %4 = tail call { i128, i128 } asm "clcl $0, $1", "=r,=r,0,1"(i128 %u1.sroa.0.0.insert.insert, i128 %u2.sroa.0.0.insert.insert)44 %asmresult = extractvalue { i128, i128 } %4, 045 %asmresult11 = extractvalue { i128, i128 } %4, 146 %5 = or i128 %asmresult, %asmresult1147 %6 = and i128 %5, 1677721548 %7 = icmp eq i128 %6, 049 %land.ext = zext i1 %7 to i3250 ret i32 %land.ext51}52 53; Test a phys-reg def.54define void @fun1(ptr %Src, ptr %Dst) {55; CHECK-LABEL: fun1:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: #APP58; CHECK-NEXT: BLA %r459; CHECK-NEXT: #NO_APP60; CHECK-NEXT: stg %r5, 8(%r3)61; CHECK-NEXT: stg %r4, 0(%r3)62; CHECK-NEXT: br %r1463entry:64 %IAsm = call i128 asm "BLA $0", "={r4}"()65 store volatile i128 %IAsm, ptr %Dst66 ret void67}68 69; Test a phys-reg use.70define void @fun2(ptr %Src, ptr %Dst) {71; CHECK-LABEL: fun2:72; CHECK: # %bb.0: # %entry73; CHECK-NEXT: lg %r5, 8(%r2)74; CHECK-NEXT: lg %r4, 0(%r2)75; CHECK-NEXT: #APP76; CHECK-NEXT: BLA %r477; CHECK-NEXT: #NO_APP78; CHECK-NEXT: br %r1479entry:80 %L = load i128, ptr %Src81 call void asm "BLA $0", "{r4}"(i128 %L)82 ret void83}84 85; Test phys-reg use and phys-reg def.86define void @fun3(ptr %Src, ptr %Dst) {87; CHECK-LABEL: fun3:88; CHECK: # %bb.0: # %entry89; CHECK-NEXT: lg %r1, 8(%r2)90; CHECK-NEXT: lg %r0, 0(%r2)91; CHECK-NEXT: #APP92; CHECK-NEXT: BLA %r4, %r093; CHECK-NEXT: #NO_APP94; CHECK-NEXT: stg %r5, 8(%r3)95; CHECK-NEXT: stg %r4, 0(%r3)96; CHECK-NEXT: br %r1497entry:98 %L = load i128, ptr %Src99 %IAsm = call i128 asm "BLA $0, $1", "={r4},{r0}"(i128 %L)100 store volatile i128 %IAsm, ptr %Dst101 ret void102}103 104; Test a tied phys-reg.105define void @fun4(ptr %Src, ptr %Dst) {106; CHECK-LABEL: fun4:107; CHECK: # %bb.0: # %entry108; CHECK-NEXT: lg %r5, 8(%r2)109; CHECK-NEXT: lg %r4, 0(%r2)110; CHECK-NEXT: #APP111; CHECK-NEXT: BLA %r4, %r4112; CHECK-NEXT: #NO_APP113; CHECK-NEXT: stg %r5, 8(%r3)114; CHECK-NEXT: stg %r4, 0(%r3)115; CHECK-NEXT: br %r14116entry:117 %L = load i128, ptr %Src118 %IAsm = call i128 asm "BLA $0, $1", "={r4},0"(i128 %L)119 store volatile i128 %IAsm, ptr %Dst120 ret void121}122 123; Test access of the odd register using 'N'.124define i64 @fun5(i64 %b) {125; CHECK-LABEL: fun5:126; CHECK: # %bb.0: # %entry127; CHECK-NEXT: lgr %r1, %r2128; CHECK-NEXT: lghi %r0, 0129; CHECK-NEXT: #APP130; CHECK-NEXT: lgr %r2,%r1131; CHECK-NEXT: #NO_APP132; CHECK-NEXT: br %r14133entry:134 %Ins = zext i64 %b to i128135 %Res = tail call i64 asm "\09lgr\09$0,${1:N}", "=d,d"(i128 %Ins)136 ret i64 %Res137}138 139; Test 'N' with multiple accesses to the same operand and i128 result.140@V128 = global i128 0, align 16141define i32 @fun6() {142; CHECK-LABEL: fun6:143; CHECK: # %bb.0: # %entry144; CHECK-NEXT: lgrl %r1, V128@GOT145; CHECK-NEXT: lg %r3, 8(%r1)146; CHECK-NEXT: lg %r2, 0(%r1)147; CHECK-NEXT: #APP148; CHECK-NEXT: ltgr %r3,%r3149; CHECK-NEXT: #NO_APP150; CHECK-NEXT: stg %r2, 0(%r1)151; CHECK-NEXT: stg %r3, 8(%r1)152; CHECK-NEXT: br %r14153entry:154 %0 = load i128, ptr @V128155 %1 = tail call i128 asm "ltgr ${0:N},${0:N}", "=&d,0"(i128 %0)156 store i128 %1, ptr @V128157 ret i32 undef158}159