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1; Test insertions of i32s into the low half of an i64.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5; Insertion of an i32 can be done using LR.6define i64 @f1(i64 %a, i32 %b) {7; CHECK-LABEL: f1:8; CHECK-NOT: {{%r[23]}}9; CHECK: lr %r2, %r310; CHECK: br %r1411 %low = zext i32 %b to i6412 %high = and i64 %a, -429496729613 %res = or i64 %high, %low14 ret i64 %res15}16 17; ... and again with the operands reversed.18define i64 @f2(i64 %a, i32 %b) {19; CHECK-LABEL: f2:20; CHECK-NOT: {{%r[23]}}21; CHECK: lr %r2, %r322; CHECK: br %r1423 %low = zext i32 %b to i6424 %high = and i64 %a, -429496729625 %res = or i64 %low, %high26 ret i64 %res27}28 29; Like f1, but with "in register" zero extension.30define i64 @f3(i64 %a, i64 %b) {31; CHECK-LABEL: f3:32; CHECK-NOT: {{%r[23]}}33; CHECK: lr %r2, %r334; CHECK: br %r1435 %low = and i64 %b, 429496729536 %high = and i64 %a, -429496729637 %res = or i64 %high, %low38 ret i64 %res39}40 41; ... and again with the operands reversed.42define i64 @f4(i64 %a, i64 %b) {43; CHECK-LABEL: f4:44; CHECK-NOT: {{%r[23]}}45; CHECK: lr %r2, %r346; CHECK: br %r1447 %low = and i64 %b, 429496729548 %high = and i64 %a, -429496729649 %res = or i64 %low, %high50 ret i64 %res51}52 53; Unary operations can be done directly into the low half.54define i64 @f5(i64 %a, i32 %b) {55; CHECK-LABEL: f5:56; CHECK-NOT: {{%r[23]}}57; CHECK: lcr %r2, %r358; CHECK: br %r1459 %neg = sub i32 0, %b60 %low = zext i32 %neg to i6461 %high = and i64 %a, -429496729662 %res = or i64 %high, %low63 ret i64 %res64}65 66; ...likewise three-operand binary operations like RLL.67define i64 @f6(i64 %a, i32 %b) {68; CHECK-LABEL: f6:69; CHECK-NOT: {{%r[23]}}70; CHECK: rll %r2, %r3, 171; CHECK: br %r1472 %parta = shl i32 %b, 173 %partb = lshr i32 %b, 3174 %rot = or i32 %parta, %partb75 %low = zext i32 %rot to i6476 %high = and i64 %a, -429496729677 %res = or i64 %low, %high78 ret i64 %res79}80 81; Loads can be done directly into the low half. The range of L is checked82; in the move tests.83define i64 @f7(i64 %a, ptr %src) {84; CHECK-LABEL: f7:85; CHECK-NOT: {{%r[23]}}86; CHECK: l %r2, 0(%r3)87; CHECK: br %r1488 %b = load i32, ptr %src89 %low = zext i32 %b to i6490 %high = and i64 %a, -429496729691 %res = or i64 %high, %low92 ret i64 %res93}94 95; ...likewise extending loads.96define i64 @f8(i64 %a, ptr %src) {97; CHECK-LABEL: f8:98; CHECK-NOT: {{%r[23]}}99; CHECK: lb %r2, 0(%r3)100; CHECK: br %r14101 %byte = load i8, ptr %src102 %b = sext i8 %byte to i32103 %low = zext i32 %b to i64104 %high = and i64 %a, -4294967296105 %res = or i64 %high, %low106 ret i64 %res107}108 109; Check a case like f1 in which there is no AND. We simply know from context110; that the upper half of one OR operand and the lower half of the other are111; both clear.112define i64 @f9(i64 %a, i32 %b) {113; CHECK-LABEL: f9:114; CHECK: sllg %r2, %r2, 32115; CHECK: lr %r2, %r3116; CHECK: br %r14117 %shift = shl i64 %a, 32118 %low = zext i32 %b to i64119 %or = or i64 %shift, %low120 ret i64 %or121}122 123; ...and again with the operands reversed.124define i64 @f10(i64 %a, i32 %b) {125; CHECK-LABEL: f10:126; CHECK: sllg %r2, %r2, 32127; CHECK: lr %r2, %r3128; CHECK: br %r14129 %shift = shl i64 %a, 32130 %low = zext i32 %b to i64131 %or = or i64 %low, %shift132 ret i64 %or133}134 135; Like f9, but with "in register" zero extension.136define i64 @f11(i64 %a, i64 %b) {137; CHECK-LABEL: f11:138; CHECK: lr %r2, %r3139; CHECK: br %r14140 %shift = shl i64 %a, 32141 %low = and i64 %b, 4294967295142 %or = or i64 %shift, %low143 ret i64 %or144}145 146; ...and again with the operands reversed.147define i64 @f12(i64 %a, i64 %b) {148; CHECK-LABEL: f12:149; CHECK: lr %r2, %r3150; CHECK: br %r14151 %shift = shl i64 %a, 32152 %low = and i64 %b, 4294967295153 %or = or i64 %low, %shift154 ret i64 %or155}156 157; Like f9, but for larger shifts than 32.158define i64 @f13(i64 %a, i32 %b) {159; CHECK-LABEL: f13:160; CHECK: sllg %r2, %r2, 60161; CHECK: lr %r2, %r3162; CHECK: br %r14163 %shift = shl i64 %a, 60164 %low = zext i32 %b to i64165 %or = or i64 %shift, %low166 ret i64 %or167}168 169; We previously wrongly removed the upper AND as dead.170define i64 @f14(i64 %a, i64 %b) {171; CHECK-LABEL: f14:172; CHECK: risbg {{%r[0-5]}}, %r2, 6, 134, 0173; CHECK: br %r14174 %and1 = and i64 %a, 144115188075855872175 %and2 = and i64 %b, 15176 %or = or i64 %and1, %and2177 %res = icmp eq i64 %or, 0178 %ext = sext i1 %res to i64179 ret i64 %ext180}181 182; Check another representation of f8.183define i64 @f15(i64 %a, ptr %src) {184; CHECK-LABEL: f15:185; CHECK-NOT: {{%r[23]}}186; CHECK: lb %r2, 0(%r3)187; CHECK: br %r14188 %byte = load i8, ptr %src189 %b = sext i8 %byte to i64190 %low = and i64 %b, 4294967295191 %high = and i64 %a, -4294967296192 %res = or i64 %high, %low193 ret i64 %res194}195