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1; Test 64-bit addition in which the second operand is variable.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s --check-prefixes=CHECK,Z104; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s --check-prefixes=CHECK,Z1965 6declare i64 @foo()7 8; Check AGR.9define i64 @f1(i64 %a, i64 %b) {10; CHECK-LABEL: f1:11; CHECK: agr %r2, %r312; CHECK: br %r1413 %add = add i64 %a, %b14 ret i64 %add15}16 17; Check AG with no displacement.18define i64 @f2(i64 %a, ptr %src) {19; CHECK-LABEL: f2:20; CHECK: ag %r2, 0(%r3)21; CHECK: br %r1422 %b = load i64, ptr %src23 %add = add i64 %a, %b24 ret i64 %add25}26 27; Check the high end of the aligned AG range.28define i64 @f3(i64 %a, ptr %src) {29; CHECK-LABEL: f3:30; CHECK: ag %r2, 524280(%r3)31; CHECK: br %r1432 %ptr = getelementptr i64, ptr %src, i64 6553533 %b = load i64, ptr %ptr34 %add = add i64 %a, %b35 ret i64 %add36}37 38; Check the next doubleword up, which needs separate address logic.39; Other sequences besides this one would be OK.40define i64 @f4(i64 %a, ptr %src) {41; CHECK-LABEL: f4:42; CHECK: agfi %r3, 52428843; CHECK: ag %r2, 0(%r3)44; CHECK: br %r1445 %ptr = getelementptr i64, ptr %src, i64 6553646 %b = load i64, ptr %ptr47 %add = add i64 %a, %b48 ret i64 %add49}50 51; Check the high end of the negative aligned AG range.52define i64 @f5(i64 %a, ptr %src) {53; CHECK-LABEL: f5:54; CHECK: ag %r2, -8(%r3)55; CHECK: br %r1456 %ptr = getelementptr i64, ptr %src, i64 -157 %b = load i64, ptr %ptr58 %add = add i64 %a, %b59 ret i64 %add60}61 62; Check the low end of the AG range.63define i64 @f6(i64 %a, ptr %src) {64; CHECK-LABEL: f6:65; CHECK: ag %r2, -524288(%r3)66; CHECK: br %r1467 %ptr = getelementptr i64, ptr %src, i64 -6553668 %b = load i64, ptr %ptr69 %add = add i64 %a, %b70 ret i64 %add71}72 73; Check the next doubleword down, which needs separate address logic.74; Other sequences besides this one would be OK.75define i64 @f7(i64 %a, ptr %src) {76; CHECK-LABEL: f7:77; CHECK: agfi %r3, -52429678; CHECK: ag %r2, 0(%r3)79; CHECK: br %r1480 %ptr = getelementptr i64, ptr %src, i64 -6553781 %b = load i64, ptr %ptr82 %add = add i64 %a, %b83 ret i64 %add84}85 86; Check that AG allows an index.87define i64 @f8(i64 %a, i64 %src, i64 %index) {88; CHECK-LABEL: f8:89; CHECK: ag %r2, 524280({{%r4,%r3|%r3,%r4}})90; CHECK: br %r1491 %add1 = add i64 %src, %index92 %add2 = add i64 %add1, 52428093 %ptr = inttoptr i64 %add2 to ptr94 %b = load i64, ptr %ptr95 %add = add i64 %a, %b96 ret i64 %add97}98 99; Check that additions of spilled values can use AG rather than AGR.100; Note: Z196 is suboptimal with one unfolded reload.101define i64 @f9(ptr %ptr0) {102; CHECK-LABEL: f9:103; CHECK: brasl %r14, foo@PLT104; Z10: ag %r2, 168(%r15)105; Z196: ag %r0, 168(%r15)106; CHECK: br %r14107 %ptr1 = getelementptr i64, ptr %ptr0, i64 2108 %ptr2 = getelementptr i64, ptr %ptr0, i64 4109 %ptr3 = getelementptr i64, ptr %ptr0, i64 6110 %ptr4 = getelementptr i64, ptr %ptr0, i64 8111 %ptr5 = getelementptr i64, ptr %ptr0, i64 10112 %ptr6 = getelementptr i64, ptr %ptr0, i64 12113 %ptr7 = getelementptr i64, ptr %ptr0, i64 14114 %ptr8 = getelementptr i64, ptr %ptr0, i64 16115 %ptr9 = getelementptr i64, ptr %ptr0, i64 18116 117 %val0 = load i64, ptr %ptr0118 %val1 = load i64, ptr %ptr1119 %val2 = load i64, ptr %ptr2120 %val3 = load i64, ptr %ptr3121 %val4 = load i64, ptr %ptr4122 %val5 = load i64, ptr %ptr5123 %val6 = load i64, ptr %ptr6124 %val7 = load i64, ptr %ptr7125 %val8 = load i64, ptr %ptr8126 %val9 = load i64, ptr %ptr9127 128 %ret = call i64 @foo()129 130 %add0 = add i64 %ret, %val0131 %add1 = add i64 %add0, %val1132 %add2 = add i64 %add1, %val2133 %add3 = add i64 %add2, %val3134 %add4 = add i64 %add3, %val4135 %add5 = add i64 %add4, %val5136 %add6 = add i64 %add5, %val6137 %add7 = add i64 %add6, %val7138 %add8 = add i64 %add7, %val8139 %add9 = add i64 %add8, %val9140 141 ret i64 %add9142}143