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1; Test 128-bit addition in which the second operand is variable.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s5 6declare ptr@foo()7 8; Test register addition.9define void @f1(ptr %ptr) {10; CHECK-LABEL: f1:11; CHECK: algr12; CHECK: alcgr13; CHECK: br %r1414 %value = load i128, ptr %ptr15 %add = add i128 %value, %value16 store i128 %add, ptr %ptr17 ret void18}19 20; Test memory addition with no offset. Making the load of %a volatile21; should force the memory operand to be %b.22define void @f2(ptr %aptr, i64 %addr) {23; CHECK-LABEL: f2:24; CHECK: alg {{%r[0-5]}}, 8(%r3)25; CHECK: alcg {{%r[0-5]}}, 0(%r3)26; CHECK: br %r1427 %bptr = inttoptr i64 %addr to ptr28 %a = load volatile i128, ptr %aptr29 %b = load i128, ptr %bptr30 %add = add i128 %a, %b31 store i128 %add, ptr %aptr32 ret void33}34 35; Test the highest aligned offset that is in range of both ALG and ALCG.36define void @f3(ptr %aptr, i64 %base) {37; CHECK-LABEL: f3:38; CHECK: alg {{%r[0-5]}}, 524280(%r3)39; CHECK: alcg {{%r[0-5]}}, 524272(%r3)40; CHECK: br %r1441 %addr = add i64 %base, 52427242 %bptr = inttoptr i64 %addr to ptr43 %a = load volatile i128, ptr %aptr44 %b = load i128, ptr %bptr45 %add = add i128 %a, %b46 store i128 %add, ptr %aptr47 ret void48}49 50; Test the next doubleword up, which requires separate address logic for ALG.51define void @f4(ptr %aptr, i64 %base) {52; CHECK-LABEL: f4:53; CHECK: lay [[BASE:%r[1-5]]], 524280(%r3)54; CHECK: alg {{%r[0-5]}}, 8([[BASE]])55; CHECK: alcg {{%r[0-5]}}, 524280(%r3)56; CHECK: br %r1457 %addr = add i64 %base, 52428058 %bptr = inttoptr i64 %addr to ptr59 %a = load volatile i128, ptr %aptr60 %b = load i128, ptr %bptr61 %add = add i128 %a, %b62 store i128 %add, ptr %aptr63 ret void64}65 66; Test the next doubleword after that, which requires separate logic for67; both instructions.68define void @f5(ptr %aptr, i64 %base) {69; CHECK-LABEL: f5:70; CHECK: alg {{%r[0-5]}}, 8({{%r[1-5]}})71; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})72; CHECK: br %r1473 %addr = add i64 %base, 52428874 %bptr = inttoptr i64 %addr to ptr75 %a = load volatile i128, ptr %aptr76 %b = load i128, ptr %bptr77 %add = add i128 %a, %b78 store i128 %add, ptr %aptr79 ret void80}81 82; Test the lowest displacement that is in range of both ALG and ALCG.83define void @f6(ptr %aptr, i64 %base) {84; CHECK-LABEL: f6:85; CHECK: alg {{%r[0-5]}}, -524280(%r3)86; CHECK: alcg {{%r[0-5]}}, -524288(%r3)87; CHECK: br %r1488 %addr = add i64 %base, -52428889 %bptr = inttoptr i64 %addr to ptr90 %a = load volatile i128, ptr %aptr91 %b = load i128, ptr %bptr92 %add = add i128 %a, %b93 store i128 %add, ptr %aptr94 ret void95}96 97; Test the next doubleword down, which is out of range of the ALCG.98define void @f7(ptr %aptr, i64 %base) {99; CHECK-LABEL: f7:100; CHECK: alg {{%r[0-5]}}, -524288(%r3)101; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})102; CHECK: br %r14103 %addr = add i64 %base, -524296104 %bptr = inttoptr i64 %addr to ptr105 %a = load volatile i128, ptr %aptr106 %b = load i128, ptr %bptr107 %add = add i128 %a, %b108 store i128 %add, ptr %aptr109 ret void110}111 112; Check that additions of spilled values can use ALG and ALCG rather than113; ALGR and ALCGR.114define void @f8(ptr %ptr0) {115; CHECK-LABEL: f8:116; CHECK: brasl %r14, foo@PLT117; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15)118; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15)119; CHECK: br %r14120 %ptr1 = getelementptr i128, ptr %ptr0, i128 2121 %ptr2 = getelementptr i128, ptr %ptr0, i128 4122 %ptr3 = getelementptr i128, ptr %ptr0, i128 6123 %ptr4 = getelementptr i128, ptr %ptr0, i128 8124 %ptr5 = getelementptr i128, ptr %ptr0, i128 10125 126 %val0 = load i128, ptr %ptr0127 %val1 = load i128, ptr %ptr1128 %val2 = load i128, ptr %ptr2129 %val3 = load i128, ptr %ptr3130 %val4 = load i128, ptr %ptr4131 %val5 = load i128, ptr %ptr5132 133 %retptr = call ptr@foo()134 135 %ret = load i128, ptr %retptr136 %add0 = add i128 %ret, %val0137 %add1 = add i128 %add0, %val1138 %add2 = add i128 %add1, %val2139 %add3 = add i128 %add2, %val3140 %add4 = add i128 %add3, %val4141 %add5 = add i128 %add4, %val5142 store i128 %add5, ptr %retptr143 144 ret void145}146