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1; Test additions between an i64 and a sign-extended i16 on z14.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s4 5declare i64 @foo()6 7; Check AGH with no displacement.8define i64 @f1(i64 %a, ptr %src) {9; CHECK-LABEL: f1:10; CHECK: agh %r2, 0(%r3)11; CHECK: br %r1412 %b = load i16, ptr %src13 %bext = sext i16 %b to i6414 %add = add i64 %a, %bext15 ret i64 %add16}17 18; Check the high end of the aligned AGH range.19define i64 @f2(i64 %a, ptr %src) {20; CHECK-LABEL: f2:21; CHECK: agh %r2, 524286(%r3)22; CHECK: br %r1423 %ptr = getelementptr i16, ptr %src, i64 26214324 %b = load i16, ptr %ptr25 %bext = sext i16 %b to i6426 %add = add i64 %a, %bext27 ret i64 %add28}29 30; Check the next word up, which needs separate address logic.31; Other sequences besides this one would be OK.32define i64 @f3(i64 %a, ptr %src) {33; CHECK-LABEL: f3:34; CHECK: agfi %r3, 52428835; CHECK: agh %r2, 0(%r3)36; CHECK: br %r1437 %ptr = getelementptr i16, ptr %src, i64 26214438 %b = load i16, ptr %ptr39 %bext = sext i16 %b to i6440 %add = add i64 %a, %bext41 ret i64 %add42}43 44; Check the high end of the negative aligned AGH range.45define i64 @f4(i64 %a, ptr %src) {46; CHECK-LABEL: f4:47; CHECK: agh %r2, -2(%r3)48; CHECK: br %r1449 %ptr = getelementptr i16, ptr %src, i64 -150 %b = load i16, ptr %ptr51 %bext = sext i16 %b to i6452 %add = add i64 %a, %bext53 ret i64 %add54}55 56; Check the low end of the AGH range.57define i64 @f5(i64 %a, ptr %src) {58; CHECK-LABEL: f5:59; CHECK: agh %r2, -524288(%r3)60; CHECK: br %r1461 %ptr = getelementptr i16, ptr %src, i64 -26214462 %b = load i16, ptr %ptr63 %bext = sext i16 %b to i6464 %add = add i64 %a, %bext65 ret i64 %add66}67 68; Check the next word down, which needs separate address logic.69; Other sequences besides this one would be OK.70define i64 @f6(i64 %a, ptr %src) {71; CHECK-LABEL: f6:72; CHECK: agfi %r3, -52429073; CHECK: agh %r2, 0(%r3)74; CHECK: br %r1475 %ptr = getelementptr i16, ptr %src, i64 -26214576 %b = load i16, ptr %ptr77 %bext = sext i16 %b to i6478 %add = add i64 %a, %bext79 ret i64 %add80}81 82; Check that AGH allows an index.83define i64 @f7(i64 %a, i64 %src, i64 %index) {84; CHECK-LABEL: f7:85; CHECK: agh %r2, 524284({{%r4,%r3|%r3,%r4}})86; CHECK: br %r1487 %add1 = add i64 %src, %index88 %add2 = add i64 %add1, 52428489 %ptr = inttoptr i64 %add2 to ptr90 %b = load i16, ptr %ptr91 %bext = sext i16 %b to i6492 %add = add i64 %a, %bext93 ret i64 %add94}95 96