18 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test 128-bit addition in vector registers on z13 and later3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s6 7define i128 @f1(i128 %a, i128 %b) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl %v0, 0(%r4), 311; CHECK-NEXT: vl %v1, 0(%r3), 312; CHECK-NEXT: vaq %v0, %v1, %v013; CHECK-NEXT: vst %v0, 0(%r2), 314; CHECK-NEXT: br %r1415 %res = add i128 %a, %b16 ret i128 %res17}18