166 lines · plain
1; Test 32-bit signed comparison in which the second operand is sign-extended2; from an i16 memory value.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s5 6; Check the low end of the CH range.7define void @f1(i32 %lhs, ptr %src, ptr %dst) {8; CHECK-LABEL: f1:9; CHECK: ch %r2, 0(%r3)10; CHECK: br %r1411 %half = load i16, ptr %src12 %rhs = sext i16 %half to i3213 %cond = icmp slt i32 %lhs, %rhs14 %res = select i1 %cond, i32 100, i32 20015 store i32 %res, ptr %dst16 ret void17}18 19; Check the high end of the aligned CH range.20define void @f2(i32 %lhs, ptr %src, ptr %dst) {21; CHECK-LABEL: f2:22; CHECK: ch %r2, 4094(%r3)23; CHECK: br %r1424 %ptr = getelementptr i16, ptr %src, i64 204725 %half = load i16, ptr %ptr26 %rhs = sext i16 %half to i3227 %cond = icmp slt i32 %lhs, %rhs28 %res = select i1 %cond, i32 100, i32 20029 store i32 %res, ptr %dst30 ret void31}32 33; Check the next halfword up, which should use CHY instead of CH.34define void @f3(i32 %lhs, ptr %src, ptr %dst) {35; CHECK-LABEL: f3:36; CHECK: chy %r2, 4096(%r3)37; CHECK: br %r1438 %ptr = getelementptr i16, ptr %src, i64 204839 %half = load i16, ptr %ptr40 %rhs = sext i16 %half to i3241 %cond = icmp slt i32 %lhs, %rhs42 %res = select i1 %cond, i32 100, i32 20043 store i32 %res, ptr %dst44 ret void45}46 47; Check the high end of the aligned CHY range.48define void @f4(i32 %lhs, ptr %src, ptr %dst) {49; CHECK-LABEL: f4:50; CHECK: chy %r2, 524286(%r3)51; CHECK: br %r1452 %ptr = getelementptr i16, ptr %src, i64 26214353 %half = load i16, ptr %ptr54 %rhs = sext i16 %half to i3255 %cond = icmp slt i32 %lhs, %rhs56 %res = select i1 %cond, i32 100, i32 20057 store i32 %res, ptr %dst58 ret void59}60 61; Check the next halfword up, which needs separate address logic.62; Other sequences besides this one would be OK.63define void @f5(i32 %lhs, ptr %src, ptr %dst) {64; CHECK-LABEL: f5:65; CHECK: agfi %r3, 52428866; CHECK: ch %r2, 0(%r3)67; CHECK: br %r1468 %ptr = getelementptr i16, ptr %src, i64 26214469 %half = load i16, ptr %ptr70 %rhs = sext i16 %half to i3271 %cond = icmp slt i32 %lhs, %rhs72 %res = select i1 %cond, i32 100, i32 20073 store i32 %res, ptr %dst74 ret void75}76 77; Check the high end of the negative aligned CHY range.78define void @f6(i32 %lhs, ptr %src, ptr %dst) {79; CHECK-LABEL: f6:80; CHECK: chy %r2, -2(%r3)81; CHECK: br %r1482 %ptr = getelementptr i16, ptr %src, i64 -183 %half = load i16, ptr %ptr84 %rhs = sext i16 %half to i3285 %cond = icmp slt i32 %lhs, %rhs86 %res = select i1 %cond, i32 100, i32 20087 store i32 %res, ptr %dst88 ret void89}90 91; Check the low end of the CHY range.92define void @f7(i32 %lhs, ptr %src, ptr %dst) {93; CHECK-LABEL: f7:94; CHECK: chy %r2, -524288(%r3)95; CHECK: br %r1496 %ptr = getelementptr i16, ptr %src, i64 -26214497 %half = load i16, ptr %ptr98 %rhs = sext i16 %half to i3299 %cond = icmp slt i32 %lhs, %rhs100 %res = select i1 %cond, i32 100, i32 200101 store i32 %res, ptr %dst102 ret void103}104 105; Check the next halfword down, which needs separate address logic.106; Other sequences besides this one would be OK.107define void @f8(i32 %lhs, ptr %src, ptr %dst) {108; CHECK-LABEL: f8:109; CHECK: agfi %r3, -524290110; CHECK: ch %r2, 0(%r3)111; CHECK: br %r14112 %ptr = getelementptr i16, ptr %src, i64 -262145113 %half = load i16, ptr %ptr114 %rhs = sext i16 %half to i32115 %cond = icmp slt i32 %lhs, %rhs116 %res = select i1 %cond, i32 100, i32 200117 store i32 %res, ptr %dst118 ret void119}120 121; Check that CH allows an index.122define void @f9(i32 %lhs, i64 %base, i64 %index, ptr %dst) {123; CHECK-LABEL: f9:124; CHECK: ch %r2, 4094({{%r4,%r3|%r3,%r4}})125; CHECK: br %r14126 %add1 = add i64 %base, %index127 %add2 = add i64 %add1, 4094128 %ptr = inttoptr i64 %add2 to ptr129 %half = load i16, ptr %ptr130 %rhs = sext i16 %half to i32131 %cond = icmp slt i32 %lhs, %rhs132 %res = select i1 %cond, i32 100, i32 200133 store i32 %res, ptr %dst134 ret void135}136 137; Check that CHY allows an index.138define void @f10(i32 %lhs, i64 %base, i64 %index, ptr %dst) {139; CHECK-LABEL: f10:140; CHECK: chy %r2, 4096({{%r4,%r3|%r3,%r4}})141; CHECK: br %r14142 %add1 = add i64 %base, %index143 %add2 = add i64 %add1, 4096144 %ptr = inttoptr i64 %add2 to ptr145 %half = load i16, ptr %ptr146 %rhs = sext i16 %half to i32147 %cond = icmp slt i32 %lhs, %rhs148 %res = select i1 %cond, i32 100, i32 200149 store i32 %res, ptr %dst150 ret void151}152 153; Check the comparison can be reversed if that allows CH to be used.154define double @f11(double %a, double %b, i32 %rhs, ptr %src) {155; CHECK-LABEL: f11:156; CHECK: ch %r2, 0(%r3)157; CHECK-NEXT: bhr %r14158; CHECK: ldr %f0, %f2159; CHECK: br %r14160 %half = load i16, ptr %src161 %lhs = sext i16 %half to i32162 %cond = icmp slt i32 %lhs, %rhs163 %res = select i1 %cond, double %a, double %b164 ret double %res165}166