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1; Test 64-bit signed comparison in which the second operand is sign-extended2; from an i16 memory value.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s5 6; Check CGH with no displacement.7define void @f1(i64 %lhs, ptr %src, ptr %dst) {8; CHECK-LABEL: f1:9; CHECK: cgh %r2, 0(%r3)10; CHECK: br %r1411 %half = load i16, ptr %src12 %rhs = sext i16 %half to i6413 %cond = icmp slt i64 %lhs, %rhs14 %res = select i1 %cond, i64 100, i64 20015 store i64 %res, ptr %dst16 ret void17}18 19; Check the high end of the aligned CGH range.20define void @f2(i64 %lhs, ptr %src, ptr %dst) {21; CHECK-LABEL: f2:22; CHECK: cgh %r2, 524286(%r3)23; CHECK: br %r1424 %ptr = getelementptr i16, ptr %src, i64 26214325 %half = load i16, ptr %ptr26 %rhs = sext i16 %half to i6427 %cond = icmp slt i64 %lhs, %rhs28 %res = select i1 %cond, i64 100, i64 20029 store i64 %res, ptr %dst30 ret void31}32 33; Check the next halfword up, which needs separate address logic.34; Other sequences besides this one would be OK.35define void @f3(i64 %lhs, ptr %src, ptr %dst) {36; CHECK-LABEL: f3:37; CHECK: agfi %r3, 52428838; CHECK: cgh %r2, 0(%r3)39; CHECK: br %r1440 %ptr = getelementptr i16, ptr %src, i64 26214441 %half = load i16, ptr %ptr42 %rhs = sext i16 %half to i6443 %cond = icmp slt i64 %lhs, %rhs44 %res = select i1 %cond, i64 100, i64 20045 store i64 %res, ptr %dst46 ret void47}48 49; Check the high end of the negative aligned CGH range.50define void @f4(i64 %lhs, ptr %src, ptr %dst) {51; CHECK-LABEL: f4:52; CHECK: cgh %r2, -2(%r3)53; CHECK: br %r1454 %ptr = getelementptr i16, ptr %src, i64 -155 %half = load i16, ptr %ptr56 %rhs = sext i16 %half to i6457 %cond = icmp slt i64 %lhs, %rhs58 %res = select i1 %cond, i64 100, i64 20059 store i64 %res, ptr %dst60 ret void61}62 63; Check the low end of the CGH range.64define void @f5(i64 %lhs, ptr %src, ptr %dst) {65; CHECK-LABEL: f5:66; CHECK: cgh %r2, -524288(%r3)67; CHECK: br %r1468 %ptr = getelementptr i16, ptr %src, i64 -26214469 %half = load i16, ptr %ptr70 %rhs = sext i16 %half to i6471 %cond = icmp slt i64 %lhs, %rhs72 %res = select i1 %cond, i64 100, i64 20073 store i64 %res, ptr %dst74 ret void75}76 77; Check the next halfword down, which needs separate address logic.78; Other sequences besides this one would be OK.79define void @f6(i64 %lhs, ptr %src, ptr %dst) {80; CHECK-LABEL: f6:81; CHECK: agfi %r3, -52429082; CHECK: cgh %r2, 0(%r3)83; CHECK: br %r1484 %ptr = getelementptr i16, ptr %src, i64 -26214585 %half = load i16, ptr %ptr86 %rhs = sext i16 %half to i6487 %cond = icmp slt i64 %lhs, %rhs88 %res = select i1 %cond, i64 100, i64 20089 store i64 %res, ptr %dst90 ret void91}92 93; Check that CGH allows an index.94define void @f7(i64 %lhs, i64 %base, i64 %index, ptr %dst) {95; CHECK-LABEL: f7:96; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}})97; CHECK: br %r1498 %add1 = add i64 %base, %index99 %add2 = add i64 %add1, 4096100 %ptr = inttoptr i64 %add2 to ptr101 %half = load i16, ptr %ptr102 %rhs = sext i16 %half to i64103 %cond = icmp slt i64 %lhs, %rhs104 %res = select i1 %cond, i64 100, i64 200105 store i64 %res, ptr %dst106 ret void107}108 109; Check the comparison can be reversed if that allows CGH to be used.110define double @f8(double %a, double %b, i64 %rhs, ptr %src) {111; CHECK-LABEL: f8:112; CHECK: cgh %r2, 0(%r3)113; CHECK-NEXT: bhr %r14114; CHECK: ldr %f0, %f2115; CHECK: br %r14116 %half = load i16, ptr %src117 %lhs = sext i16 %half to i64118 %cond = icmp slt i64 %lhs, %rhs119 %res = select i1 %cond, double %a, double %b120 ret double %res121}122