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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test 128-bit comparisons in vector registers on z133;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s5 6; Equality comparison.7define i64 @f1(i128 %value1, i128 %value2, i64 %a, i64 %b) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl %v0, 0(%r3), 311; CHECK-NEXT: vl %v1, 0(%r2), 312; CHECK-NEXT: vceqgs %v0, %v1, %v013; CHECK-NEXT: locgrnhe %r4, %r514; CHECK-NEXT: lgr %r2, %r415; CHECK-NEXT: br %r1416 %cond = icmp eq i128 %value1, %value217 %res = select i1 %cond, i64 %a, i64 %b18 ret i64 %res19}20 21; Inequality comparison.22define i64 @f2(i128 %value1, i128 %value2, i64 %a, i64 %b) {23; CHECK-LABEL: f2:24; CHECK: # %bb.0:25; CHECK-NEXT: vl %v0, 0(%r3), 326; CHECK-NEXT: vl %v1, 0(%r2), 327; CHECK-NEXT: vceqgs %v0, %v1, %v028; CHECK-NEXT: locgre %r4, %r529; CHECK-NEXT: lgr %r2, %r430; CHECK-NEXT: br %r1431 %cond = icmp ne i128 %value1, %value232 %res = select i1 %cond, i64 %a, i64 %b33 ret i64 %res34}35 36; Signed greater-than comparison.37define i64 @f3(i128 %value1, i128 %value2, i64 %a, i64 %b) {38; CHECK-LABEL: f3:39; CHECK: # %bb.0:40; CHECK-NEXT: vl %v0, 0(%r3), 341; CHECK-NEXT: vl %v1, 0(%r2), 342; CHECK-NEXT: vecg %v0, %v143; CHECK-NEXT: jlh .LBB2_244; CHECK-NEXT: # %bb.1:45; CHECK-NEXT: vchlgs %v0, %v1, %v046; CHECK-NEXT: .LBB2_2:47; CHECK-NEXT: locgrl %r5, %r448; CHECK-NEXT: lgr %r2, %r549; CHECK-NEXT: br %r1450 %cond = icmp sgt i128 %value1, %value251 %res = select i1 %cond, i64 %a, i64 %b52 ret i64 %res53}54 55; Signed less-than comparison.56define i64 @f4(i128 %value1, i128 %value2, i64 %a, i64 %b) {57; CHECK-LABEL: f4:58; CHECK: # %bb.0:59; CHECK-NEXT: vl %v0, 0(%r2), 360; CHECK-NEXT: vl %v1, 0(%r3), 361; CHECK-NEXT: vecg %v0, %v162; CHECK-NEXT: jlh .LBB3_263; CHECK-NEXT: # %bb.1:64; CHECK-NEXT: vchlgs %v0, %v1, %v065; CHECK-NEXT: .LBB3_2:66; CHECK-NEXT: locgrl %r5, %r467; CHECK-NEXT: lgr %r2, %r568; CHECK-NEXT: br %r1469 %cond = icmp slt i128 %value1, %value270 %res = select i1 %cond, i64 %a, i64 %b71 ret i64 %res72}73 74; Signed greater-or-equal comparison.75define i64 @f5(i128 %value1, i128 %value2, i64 %a, i64 %b) {76; CHECK-LABEL: f5:77; CHECK: # %bb.0:78; CHECK-NEXT: vl %v0, 0(%r2), 379; CHECK-NEXT: vl %v1, 0(%r3), 380; CHECK-NEXT: vecg %v0, %v181; CHECK-NEXT: jlh .LBB4_282; CHECK-NEXT: # %bb.1:83; CHECK-NEXT: vchlgs %v0, %v1, %v084; CHECK-NEXT: .LBB4_2:85; CHECK-NEXT: locgrnl %r5, %r486; CHECK-NEXT: lgr %r2, %r587; CHECK-NEXT: br %r1488 %cond = icmp sge i128 %value1, %value289 %res = select i1 %cond, i64 %a, i64 %b90 ret i64 %res91}92 93; Signed less-or-equal comparison.94define i64 @f6(i128 %value1, i128 %value2, i64 %a, i64 %b) {95; CHECK-LABEL: f6:96; CHECK: # %bb.0:97; CHECK-NEXT: vl %v0, 0(%r3), 398; CHECK-NEXT: vl %v1, 0(%r2), 399; CHECK-NEXT: vecg %v0, %v1100; CHECK-NEXT: jlh .LBB5_2101; CHECK-NEXT: # %bb.1:102; CHECK-NEXT: vchlgs %v0, %v1, %v0103; CHECK-NEXT: .LBB5_2:104; CHECK-NEXT: locgrnl %r5, %r4105; CHECK-NEXT: lgr %r2, %r5106; CHECK-NEXT: br %r14107 %cond = icmp sle i128 %value1, %value2108 %res = select i1 %cond, i64 %a, i64 %b109 ret i64 %res110}111 112; Unsigned greater-than comparison.113define i64 @f7(i128 %value1, i128 %value2, i64 %a, i64 %b) {114; CHECK-LABEL: f7:115; CHECK: # %bb.0:116; CHECK-NEXT: vl %v0, 0(%r3), 3117; CHECK-NEXT: vl %v1, 0(%r2), 3118; CHECK-NEXT: veclg %v0, %v1119; CHECK-NEXT: jlh .LBB6_2120; CHECK-NEXT: # %bb.1:121; CHECK-NEXT: vchlgs %v0, %v1, %v0122; CHECK-NEXT: .LBB6_2:123; CHECK-NEXT: locgrl %r5, %r4124; CHECK-NEXT: lgr %r2, %r5125; CHECK-NEXT: br %r14126 %cond = icmp ugt i128 %value1, %value2127 %res = select i1 %cond, i64 %a, i64 %b128 ret i64 %res129}130 131; Unsigned less-than comparison.132define i64 @f8(i128 %value1, i128 %value2, i64 %a, i64 %b) {133; CHECK-LABEL: f8:134; CHECK: # %bb.0:135; CHECK-NEXT: vl %v0, 0(%r2), 3136; CHECK-NEXT: vl %v1, 0(%r3), 3137; CHECK-NEXT: veclg %v0, %v1138; CHECK-NEXT: jlh .LBB7_2139; CHECK-NEXT: # %bb.1:140; CHECK-NEXT: vchlgs %v0, %v1, %v0141; CHECK-NEXT: .LBB7_2:142; CHECK-NEXT: locgrl %r5, %r4143; CHECK-NEXT: lgr %r2, %r5144; CHECK-NEXT: br %r14145 %cond = icmp ult i128 %value1, %value2146 %res = select i1 %cond, i64 %a, i64 %b147 ret i64 %res148}149 150; Unsigned greater-or-equal comparison.151define i64 @f9(i128 %value1, i128 %value2, i64 %a, i64 %b) {152; CHECK-LABEL: f9:153; CHECK: # %bb.0:154; CHECK-NEXT: vl %v0, 0(%r2), 3155; CHECK-NEXT: vl %v1, 0(%r3), 3156; CHECK-NEXT: veclg %v0, %v1157; CHECK-NEXT: jlh .LBB8_2158; CHECK-NEXT: # %bb.1:159; CHECK-NEXT: vchlgs %v0, %v1, %v0160; CHECK-NEXT: .LBB8_2:161; CHECK-NEXT: locgrnl %r5, %r4162; CHECK-NEXT: lgr %r2, %r5163; CHECK-NEXT: br %r14164 %cond = icmp uge i128 %value1, %value2165 %res = select i1 %cond, i64 %a, i64 %b166 ret i64 %res167}168 169; Unsigned less-or-equal comparison.170define i64 @f10(i128 %value1, i128 %value2, i64 %a, i64 %b) {171; CHECK-LABEL: f10:172; CHECK: # %bb.0:173; CHECK-NEXT: vl %v0, 0(%r3), 3174; CHECK-NEXT: vl %v1, 0(%r2), 3175; CHECK-NEXT: veclg %v0, %v1176; CHECK-NEXT: jlh .LBB9_2177; CHECK-NEXT: # %bb.1:178; CHECK-NEXT: vchlgs %v0, %v1, %v0179; CHECK-NEXT: .LBB9_2:180; CHECK-NEXT: locgrnl %r5, %r4181; CHECK-NEXT: lgr %r2, %r5182; CHECK-NEXT: br %r14183 %cond = icmp ule i128 %value1, %value2184 %res = select i1 %cond, i64 %a, i64 %b185 ret i64 %res186}187 188; Use VTM for "x & y == 0" comparison.189define i64 @f11(i128 %value1, i128 %value2, i64 %a, i64 %b) {190; CHECK-LABEL: f11:191; CHECK: # %bb.0:192; CHECK-NEXT: vl %v0, 0(%r3), 3193; CHECK-NEXT: vl %v1, 0(%r2), 3194; CHECK-NEXT: vtm %v1, %v0195; CHECK-NEXT: locgrnhe %r4, %r5196; CHECK-NEXT: lgr %r2, %r4197; CHECK-NEXT: br %r14198 %and = and i128 %value1, %value2199 %cond = icmp eq i128 %and, 0200 %res = select i1 %cond, i64 %a, i64 %b201 ret i64 %res202}203 204; Use VTM for "x & y != 0" comparison.205define i64 @f12(i128 %value1, i128 %value2, i64 %a, i64 %b) {206; CHECK-LABEL: f12:207; CHECK: # %bb.0:208; CHECK-NEXT: vl %v0, 0(%r3), 3209; CHECK-NEXT: vl %v1, 0(%r2), 3210; CHECK-NEXT: vtm %v1, %v0211; CHECK-NEXT: locgre %r4, %r5212; CHECK-NEXT: lgr %r2, %r4213; CHECK-NEXT: br %r14214 %and = and i128 %value1, %value2215 %cond = icmp ne i128 %and, 0216 %res = select i1 %cond, i64 %a, i64 %b217 ret i64 %res218}219 220; Select between i128 values.221define i128 @f13(i64 %value1, i64 %value2, i128 %a, i128 %b) {222; CHECK-LABEL: f13:223; CHECK: # %bb.0:224; CHECK-NEXT: vl %v0, 0(%r5), 3225; CHECK-NEXT: cgrje %r3, %r4, .LBB12_2226; CHECK-NEXT: # %bb.1:227; CHECK-NEXT: vl %v1, 0(%r6), 3228; CHECK-NEXT: vaq %v0, %v0, %v1229; CHECK-NEXT: .LBB12_2:230; CHECK-NEXT: vst %v0, 0(%r2), 3231; CHECK-NEXT: br %r14232 %cond = icmp eq i64 %value1, %value2233 %sum = add i128 %a, %b234 %res = select i1 %cond, i128 %a, i128 %sum235 ret i128 %res236}237 238