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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test 128-bit comparisons in vector registers on z173;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 -verify-machineinstrs | FileCheck %s5 6; Equality comparison.7define i64 @f1(i128 %value1, i128 %value2, i64 %a, i64 %b) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl %v0, 0(%r3), 311; CHECK-NEXT: vl %v1, 0(%r2), 312; CHECK-NEXT: vecq %v1, %v013; CHECK-NEXT: selgre %r2, %r4, %r514; CHECK-NEXT: br %r1415 %cond = icmp eq i128 %value1, %value216 %res = select i1 %cond, i64 %a, i64 %b17 ret i64 %res18}19 20; Inequality comparison.21define i64 @f2(i128 %value1, i128 %value2, i64 %a, i64 %b) {22; CHECK-LABEL: f2:23; CHECK: # %bb.0:24; CHECK-NEXT: vl %v0, 0(%r3), 325; CHECK-NEXT: vl %v1, 0(%r2), 326; CHECK-NEXT: vecq %v1, %v027; CHECK-NEXT: selgrlh %r2, %r4, %r528; CHECK-NEXT: br %r1429 %cond = icmp ne i128 %value1, %value230 %res = select i1 %cond, i64 %a, i64 %b31 ret i64 %res32}33 34; Signed greater-than comparison.35define i64 @f3(i128 %value1, i128 %value2, i64 %a, i64 %b) {36; CHECK-LABEL: f3:37; CHECK: # %bb.0:38; CHECK-NEXT: vl %v0, 0(%r3), 339; CHECK-NEXT: vl %v1, 0(%r2), 340; CHECK-NEXT: vecq %v1, %v041; CHECK-NEXT: selgrh %r2, %r4, %r542; CHECK-NEXT: br %r1443 %cond = icmp sgt i128 %value1, %value244 %res = select i1 %cond, i64 %a, i64 %b45 ret i64 %res46}47 48; Signed less-than comparison.49define i64 @f4(i128 %value1, i128 %value2, i64 %a, i64 %b) {50; CHECK-LABEL: f4:51; CHECK: # %bb.0:52; CHECK-NEXT: vl %v0, 0(%r3), 353; CHECK-NEXT: vl %v1, 0(%r2), 354; CHECK-NEXT: vecq %v1, %v055; CHECK-NEXT: selgrl %r2, %r4, %r556; CHECK-NEXT: br %r1457 %cond = icmp slt i128 %value1, %value258 %res = select i1 %cond, i64 %a, i64 %b59 ret i64 %res60}61 62; Signed greater-or-equal comparison.63define i64 @f5(i128 %value1, i128 %value2, i64 %a, i64 %b) {64; CHECK-LABEL: f5:65; CHECK: # %bb.0:66; CHECK-NEXT: vl %v0, 0(%r3), 367; CHECK-NEXT: vl %v1, 0(%r2), 368; CHECK-NEXT: vecq %v1, %v069; CHECK-NEXT: selgrhe %r2, %r4, %r570; CHECK-NEXT: br %r1471 %cond = icmp sge i128 %value1, %value272 %res = select i1 %cond, i64 %a, i64 %b73 ret i64 %res74}75 76; Signed less-or-equal comparison.77define i64 @f6(i128 %value1, i128 %value2, i64 %a, i64 %b) {78; CHECK-LABEL: f6:79; CHECK: # %bb.0:80; CHECK-NEXT: vl %v0, 0(%r3), 381; CHECK-NEXT: vl %v1, 0(%r2), 382; CHECK-NEXT: vecq %v1, %v083; CHECK-NEXT: selgrle %r2, %r4, %r584; CHECK-NEXT: br %r1485 %cond = icmp sle i128 %value1, %value286 %res = select i1 %cond, i64 %a, i64 %b87 ret i64 %res88}89 90; Unsigned greater-than comparison.91define i64 @f7(i128 %value1, i128 %value2, i64 %a, i64 %b) {92; CHECK-LABEL: f7:93; CHECK: # %bb.0:94; CHECK-NEXT: vl %v0, 0(%r3), 395; CHECK-NEXT: vl %v1, 0(%r2), 396; CHECK-NEXT: veclq %v1, %v097; CHECK-NEXT: selgrh %r2, %r4, %r598; CHECK-NEXT: br %r1499 %cond = icmp ugt i128 %value1, %value2100 %res = select i1 %cond, i64 %a, i64 %b101 ret i64 %res102}103 104; Unsigned less-than comparison.105define i64 @f8(i128 %value1, i128 %value2, i64 %a, i64 %b) {106; CHECK-LABEL: f8:107; CHECK: # %bb.0:108; CHECK-NEXT: vl %v0, 0(%r3), 3109; CHECK-NEXT: vl %v1, 0(%r2), 3110; CHECK-NEXT: veclq %v1, %v0111; CHECK-NEXT: selgrl %r2, %r4, %r5112; CHECK-NEXT: br %r14113 %cond = icmp ult i128 %value1, %value2114 %res = select i1 %cond, i64 %a, i64 %b115 ret i64 %res116}117 118; Unsigned greater-or-equal comparison.119define i64 @f9(i128 %value1, i128 %value2, i64 %a, i64 %b) {120; CHECK-LABEL: f9:121; CHECK: # %bb.0:122; CHECK-NEXT: vl %v0, 0(%r3), 3123; CHECK-NEXT: vl %v1, 0(%r2), 3124; CHECK-NEXT: veclq %v1, %v0125; CHECK-NEXT: selgrhe %r2, %r4, %r5126; CHECK-NEXT: br %r14127 %cond = icmp uge i128 %value1, %value2128 %res = select i1 %cond, i64 %a, i64 %b129 ret i64 %res130}131 132; Unsigned less-or-equal comparison.133define i64 @f10(i128 %value1, i128 %value2, i64 %a, i64 %b) {134; CHECK-LABEL: f10:135; CHECK: # %bb.0:136; CHECK-NEXT: vl %v0, 0(%r3), 3137; CHECK-NEXT: vl %v1, 0(%r2), 3138; CHECK-NEXT: veclq %v1, %v0139; CHECK-NEXT: selgrle %r2, %r4, %r5140; CHECK-NEXT: br %r14141 %cond = icmp ule i128 %value1, %value2142 %res = select i1 %cond, i64 %a, i64 %b143 ret i64 %res144}145 146; Select between i128 values.147define i128 @f11(i64 %value1, i64 %value2, i128 %a, i128 %b) {148; CHECK-LABEL: f11:149; CHECK: # %bb.0:150; CHECK-NEXT: vl %v0, 0(%r5), 3151; CHECK-NEXT: cgrje %r3, %r4, .LBB10_2152; CHECK-NEXT: # %bb.1:153; CHECK-NEXT: vl %v1, 0(%r6), 3154; CHECK-NEXT: vaq %v0, %v0, %v1155; CHECK-NEXT: .LBB10_2:156; CHECK-NEXT: vst %v0, 0(%r2), 3157; CHECK-NEXT: br %r14158 %cond = icmp eq i64 %value1, %value2159 %sum = add i128 %a, %b160 %res = select i1 %cond, i128 %a, i128 %sum161 ret i128 %res162}163