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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test usage of VACC/VSCBI.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=BASELINE5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s --check-prefix=Z136 7define i128 @i128_subc_1(i128 %a, i128 %b) unnamed_addr {8; BASELINE-LABEL: i128_subc_1:9; BASELINE: # %bb.0:10; BASELINE-NEXT: stmg %r14, %r15, 112(%r15)11; BASELINE-NEXT: .cfi_offset %r14, -4812; BASELINE-NEXT: .cfi_offset %r15, -4013; BASELINE-NEXT: lg %r5, 0(%r4)14; BASELINE-NEXT: lg %r14, 0(%r3)15; BASELINE-NEXT: lg %r1, 8(%r3)16; BASELINE-NEXT: clgr %r14, %r517; BASELINE-NEXT: ipm %r018; BASELINE-NEXT: clg %r1, 8(%r4)19; BASELINE-NEXT: ipm %r120; BASELINE-NEXT: cgrjlh %r14, %r5, .LBB0_221; BASELINE-NEXT: # %bb.1:22; BASELINE-NEXT: xilf %r1, 429496729523; BASELINE-NEXT: risbg %r0, %r1, 63, 191, 3624; BASELINE-NEXT: j .LBB0_325; BASELINE-NEXT: .LBB0_2:26; BASELINE-NEXT: xilf %r0, 429496729527; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 3628; BASELINE-NEXT: .LBB0_3:29; BASELINE-NEXT: llgfr %r0, %r030; BASELINE-NEXT: stg %r0, 8(%r2)31; BASELINE-NEXT: mvghi 0(%r2), 032; BASELINE-NEXT: lmg %r14, %r15, 112(%r15)33; BASELINE-NEXT: br %r1434;35; Z13-LABEL: i128_subc_1:36; Z13: # %bb.0:37; Z13-NEXT: vl %v0, 0(%r4), 338; Z13-NEXT: vl %v1, 0(%r3), 339; Z13-NEXT: vscbiq %v0, %v1, %v040; Z13-NEXT: vst %v0, 0(%r2), 341; Z13-NEXT: br %r1442 %cmp = icmp uge i128 %a, %b43 %ext = zext i1 %cmp to i12844 ret i128 %ext45}46 47define i128 @i128_subc_2(i128 %a, i128 %b) unnamed_addr {48; BASELINE-LABEL: i128_subc_2:49; BASELINE: # %bb.0:50; BASELINE-NEXT: stmg %r14, %r15, 112(%r15)51; BASELINE-NEXT: .cfi_offset %r14, -4852; BASELINE-NEXT: .cfi_offset %r15, -4053; BASELINE-NEXT: lg %r5, 0(%r4)54; BASELINE-NEXT: lg %r14, 0(%r3)55; BASELINE-NEXT: lg %r0, 8(%r3)56; BASELINE-NEXT: clgr %r14, %r557; BASELINE-NEXT: ipm %r158; BASELINE-NEXT: clg %r0, 8(%r4)59; BASELINE-NEXT: ipm %r060; BASELINE-NEXT: cgrjlh %r14, %r5, .LBB1_261; BASELINE-NEXT: # %bb.1:62; BASELINE-NEXT: afi %r0, -53687091263; BASELINE-NEXT: srl %r0, 3164; BASELINE-NEXT: j .LBB1_365; BASELINE-NEXT: .LBB1_2:66; BASELINE-NEXT: afi %r1, -53687091267; BASELINE-NEXT: srl %r1, 3168; BASELINE-NEXT: lr %r0, %r169; BASELINE-NEXT: .LBB1_3:70; BASELINE-NEXT: llgfr %r0, %r071; BASELINE-NEXT: stg %r0, 8(%r2)72; BASELINE-NEXT: mvghi 0(%r2), 073; BASELINE-NEXT: lmg %r14, %r15, 112(%r15)74; BASELINE-NEXT: br %r1475;76; Z13-LABEL: i128_subc_2:77; Z13: # %bb.0:78; Z13-NEXT: vl %v0, 0(%r3), 379; Z13-NEXT: vl %v1, 0(%r4), 380; Z13-NEXT: vscbiq %v0, %v1, %v081; Z13-NEXT: vst %v0, 0(%r2), 382; Z13-NEXT: br %r1483 %cmp = icmp ule i128 %a, %b84 %ext = zext i1 %cmp to i12885 ret i128 %ext86}87 88define i128 @i128_addc_1(i128 %a, i128 %b) {89; BASELINE-LABEL: i128_addc_1:90; BASELINE: # %bb.0:91; BASELINE-NEXT: lg %r0, 8(%r3)92; BASELINE-NEXT: lg %r1, 0(%r3)93; BASELINE-NEXT: alg %r0, 8(%r4)94; BASELINE-NEXT: alcg %r1, 0(%r4)95; BASELINE-NEXT: ipm %r096; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 3597; BASELINE-NEXT: stg %r0, 8(%r2)98; BASELINE-NEXT: mvghi 0(%r2), 099; BASELINE-NEXT: br %r14100;101; Z13-LABEL: i128_addc_1:102; Z13: # %bb.0:103; Z13-NEXT: vl %v0, 0(%r4), 3104; Z13-NEXT: vl %v1, 0(%r3), 3105; Z13-NEXT: vaccq %v0, %v1, %v0106; Z13-NEXT: vst %v0, 0(%r2), 3107; Z13-NEXT: br %r14108 %sum = add i128 %a, %b109 %cmp = icmp ult i128 %sum, %a110 %ext = zext i1 %cmp to i128111 ret i128 %ext112}113 114define i128 @i128_addc_2(i128 %a, i128 %b) {115; BASELINE-LABEL: i128_addc_2:116; BASELINE: # %bb.0:117; BASELINE-NEXT: lg %r0, 8(%r3)118; BASELINE-NEXT: lg %r1, 0(%r3)119; BASELINE-NEXT: alg %r0, 8(%r4)120; BASELINE-NEXT: alcg %r1, 0(%r4)121; BASELINE-NEXT: ipm %r0122; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35123; BASELINE-NEXT: stg %r0, 8(%r2)124; BASELINE-NEXT: mvghi 0(%r2), 0125; BASELINE-NEXT: br %r14126;127; Z13-LABEL: i128_addc_2:128; Z13: # %bb.0:129; Z13-NEXT: vl %v0, 0(%r4), 3130; Z13-NEXT: vl %v1, 0(%r3), 3131; Z13-NEXT: vaccq %v0, %v1, %v0132; Z13-NEXT: vst %v0, 0(%r2), 3133; Z13-NEXT: br %r14134 %sum = add i128 %a, %b135 %cmp = icmp ult i128 %sum, %b136 %ext = zext i1 %cmp to i128137 ret i128 %ext138}139 140define i128 @i128_addc_3(i128 %a, i128 %b) {141; BASELINE-LABEL: i128_addc_3:142; BASELINE: # %bb.0:143; BASELINE-NEXT: lg %r0, 8(%r3)144; BASELINE-NEXT: lg %r1, 0(%r3)145; BASELINE-NEXT: alg %r0, 8(%r4)146; BASELINE-NEXT: alcg %r1, 0(%r4)147; BASELINE-NEXT: ipm %r0148; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35149; BASELINE-NEXT: stg %r0, 8(%r2)150; BASELINE-NEXT: mvghi 0(%r2), 0151; BASELINE-NEXT: br %r14152;153; Z13-LABEL: i128_addc_3:154; Z13: # %bb.0:155; Z13-NEXT: vl %v0, 0(%r4), 3156; Z13-NEXT: vl %v1, 0(%r3), 3157; Z13-NEXT: vaccq %v0, %v1, %v0158; Z13-NEXT: vst %v0, 0(%r2), 3159; Z13-NEXT: br %r14160 %sum = add i128 %a, %b161 %cmp = icmp ugt i128 %a, %sum162 %ext = zext i1 %cmp to i128163 ret i128 %ext164}165 166define i128 @i128_addc_4(i128 %a, i128 %b) {167; BASELINE-LABEL: i128_addc_4:168; BASELINE: # %bb.0:169; BASELINE-NEXT: lg %r0, 8(%r3)170; BASELINE-NEXT: lg %r1, 0(%r3)171; BASELINE-NEXT: alg %r0, 8(%r4)172; BASELINE-NEXT: alcg %r1, 0(%r4)173; BASELINE-NEXT: ipm %r0174; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35175; BASELINE-NEXT: stg %r0, 8(%r2)176; BASELINE-NEXT: mvghi 0(%r2), 0177; BASELINE-NEXT: br %r14178;179; Z13-LABEL: i128_addc_4:180; Z13: # %bb.0:181; Z13-NEXT: vl %v0, 0(%r4), 3182; Z13-NEXT: vl %v1, 0(%r3), 3183; Z13-NEXT: vaccq %v0, %v1, %v0184; Z13-NEXT: vst %v0, 0(%r2), 3185; Z13-NEXT: br %r14186 %sum = add i128 %a, %b187 %cmp = icmp ugt i128 %b, %sum188 %ext = zext i1 %cmp to i128189 ret i128 %ext190}191 192define i128 @i128_addc_xor(i128 %a, i128 %b) {193; BASELINE-LABEL: i128_addc_xor:194; BASELINE: # %bb.0:195; BASELINE-NEXT: lg %r0, 8(%r4)196; BASELINE-NEXT: lg %r1, 0(%r4)197; BASELINE-NEXT: alg %r0, 8(%r3)198; BASELINE-NEXT: alcg %r1, 0(%r3)199; BASELINE-NEXT: ipm %r0200; BASELINE-NEXT: risbg %r0, %r0, 63, 191, 35201; BASELINE-NEXT: stg %r0, 8(%r2)202; BASELINE-NEXT: mvghi 0(%r2), 0203; BASELINE-NEXT: br %r14204;205; Z13-LABEL: i128_addc_xor:206; Z13: # %bb.0:207; Z13-NEXT: vl %v0, 0(%r3), 3208; Z13-NEXT: vl %v1, 0(%r4), 3209; Z13-NEXT: vaccq %v0, %v1, %v0210; Z13-NEXT: vst %v0, 0(%r2), 3211; Z13-NEXT: br %r14212 %b.not = xor i128 %b, -1213 %cmp = icmp ugt i128 %a, %b.not214 %ext = zext i1 %cmp to i128215 ret i128 %ext216}217 218define i128 @i128_addc_xor_inv(i128 %a, i128 %b) {219; BASELINE-LABEL: i128_addc_xor_inv:220; BASELINE: # %bb.0:221; BASELINE-NEXT: stmg %r14, %r15, 112(%r15)222; BASELINE-NEXT: .cfi_offset %r14, -48223; BASELINE-NEXT: .cfi_offset %r15, -40224; BASELINE-NEXT: lg %r5, 0(%r3)225; BASELINE-NEXT: lghi %r14, -1226; BASELINE-NEXT: xg %r14, 0(%r4)227; BASELINE-NEXT: lghi %r1, -1228; BASELINE-NEXT: xg %r1, 8(%r4)229; BASELINE-NEXT: clgr %r5, %r14230; BASELINE-NEXT: ipm %r0231; BASELINE-NEXT: clg %r1, 8(%r3)232; BASELINE-NEXT: ipm %r1233; BASELINE-NEXT: cgrjlh %r5, %r14, .LBB7_2234; BASELINE-NEXT: # %bb.1:235; BASELINE-NEXT: xilf %r1, 4294967295236; BASELINE-NEXT: risbg %r0, %r1, 63, 191, 36237; BASELINE-NEXT: j .LBB7_3238; BASELINE-NEXT: .LBB7_2:239; BASELINE-NEXT: afi %r0, -536870912240; BASELINE-NEXT: srl %r0, 31241; BASELINE-NEXT: .LBB7_3:242; BASELINE-NEXT: llgfr %r0, %r0243; BASELINE-NEXT: stg %r0, 8(%r2)244; BASELINE-NEXT: mvghi 0(%r2), 0245; BASELINE-NEXT: lmg %r14, %r15, 112(%r15)246; BASELINE-NEXT: br %r14247;248; Z13-LABEL: i128_addc_xor_inv:249; Z13: # %bb.0:250; Z13-NEXT: vl %v1, 0(%r4), 3251; Z13-NEXT: vl %v0, 0(%r3), 3252; Z13-NEXT: vno %v1, %v1, %v1253; Z13-NEXT: vscbiq %v0, %v1, %v0254; Z13-NEXT: vst %v0, 0(%r2), 3255; Z13-NEXT: br %r14256 %b.not = xor i128 %b, -1257 %cmp = icmp ule i128 %a, %b.not258 %ext = zext i1 %cmp to i128259 ret i128 %ext260}261