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1; Test zero extensions from a byte to an i32. The tests here2; assume z10 register pressure, without the high words being available.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s5 6; Test register extension, starting with an i32.7define i32 @f1(i32 %a) {8; CHECK-LABEL: f1:9; CHECK: llcr %r2, %r210; CHECK: br %r1411 %byte = trunc i32 %a to i812 %ext = zext i8 %byte to i3213 ret i32 %ext14}15 16; ...and again with an i64.17define i32 @f2(i64 %a) {18; CHECK-LABEL: f2:19; CHECK: llcr %r2, %r220; CHECK: br %r1421 %byte = trunc i64 %a to i822 %ext = zext i8 %byte to i3223 ret i32 %ext24}25 26; Check ANDs that are equivalent to zero extension.27define i32 @f3(i32 %a) {28; CHECK-LABEL: f3:29; CHECK: llcr %r2, %r230; CHECK: br %r1431 %ext = and i32 %a, 25532 ret i32 %ext33}34 35; Check LLC with no displacement.36define i32 @f4(ptr %src) {37; CHECK-LABEL: f4:38; CHECK: llc %r2, 0(%r2)39; CHECK: br %r1440 %byte = load i8, ptr %src41 %ext = zext i8 %byte to i3242 ret i32 %ext43}44 45; Check the high end of the LLC range.46define i32 @f5(ptr %src) {47; CHECK-LABEL: f5:48; CHECK: llc %r2, 524287(%r2)49; CHECK: br %r1450 %ptr = getelementptr i8, ptr %src, i64 52428751 %byte = load i8, ptr %ptr52 %ext = zext i8 %byte to i3253 ret i32 %ext54}55 56; Check the next byte up, which needs separate address logic.57; Other sequences besides this one would be OK.58define i32 @f6(ptr %src) {59; CHECK-LABEL: f6:60; CHECK: agfi %r2, 52428861; CHECK: llc %r2, 0(%r2)62; CHECK: br %r1463 %ptr = getelementptr i8, ptr %src, i64 52428864 %byte = load i8, ptr %ptr65 %ext = zext i8 %byte to i3266 ret i32 %ext67}68 69; Check the high end of the negative LLC range.70define i32 @f7(ptr %src) {71; CHECK-LABEL: f7:72; CHECK: llc %r2, -1(%r2)73; CHECK: br %r1474 %ptr = getelementptr i8, ptr %src, i64 -175 %byte = load i8, ptr %ptr76 %ext = zext i8 %byte to i3277 ret i32 %ext78}79 80; Check the low end of the LLC range.81define i32 @f8(ptr %src) {82; CHECK-LABEL: f8:83; CHECK: llc %r2, -524288(%r2)84; CHECK: br %r1485 %ptr = getelementptr i8, ptr %src, i64 -52428886 %byte = load i8, ptr %ptr87 %ext = zext i8 %byte to i3288 ret i32 %ext89}90 91; Check the next byte down, which needs separate address logic.92; Other sequences besides this one would be OK.93define i32 @f9(ptr %src) {94; CHECK-LABEL: f9:95; CHECK: agfi %r2, -52428996; CHECK: llc %r2, 0(%r2)97; CHECK: br %r1498 %ptr = getelementptr i8, ptr %src, i64 -52428999 %byte = load i8, ptr %ptr100 %ext = zext i8 %byte to i32101 ret i32 %ext102}103 104; Check that LLC allows an index105define i32 @f10(i64 %src, i64 %index) {106; CHECK-LABEL: f10:107; CHECK: llc %r2, 524287(%r3,%r2)108; CHECK: br %r14109 %add1 = add i64 %src, %index110 %add2 = add i64 %add1, 524287111 %ptr = inttoptr i64 %add2 to ptr112 %byte = load i8, ptr %ptr113 %ext = zext i8 %byte to i32114 ret i32 %ext115}116 117; Test a case where we spill the source of at least one LLCR. We want118; to use LLC if possible.119define void @f11(ptr %ptr) {120; CHECK-LABEL: f11:121; CHECK: llc {{%r[0-9]+}}, 179(%r15)122; CHECK: br %r14123 %val0 = load volatile i32, ptr %ptr124 %val1 = load volatile i32, ptr %ptr125 %val2 = load volatile i32, ptr %ptr126 %val3 = load volatile i32, ptr %ptr127 %val4 = load volatile i32, ptr %ptr128 %val5 = load volatile i32, ptr %ptr129 %val6 = load volatile i32, ptr %ptr130 %val7 = load volatile i32, ptr %ptr131 %val8 = load volatile i32, ptr %ptr132 %val9 = load volatile i32, ptr %ptr133 %val10 = load volatile i32, ptr %ptr134 %val11 = load volatile i32, ptr %ptr135 %val12 = load volatile i32, ptr %ptr136 %val13 = load volatile i32, ptr %ptr137 %val14 = load volatile i32, ptr %ptr138 %val15 = load volatile i32, ptr %ptr139 140 %trunc0 = trunc i32 %val0 to i8141 %trunc1 = trunc i32 %val1 to i8142 %trunc2 = trunc i32 %val2 to i8143 %trunc3 = trunc i32 %val3 to i8144 %trunc4 = trunc i32 %val4 to i8145 %trunc5 = trunc i32 %val5 to i8146 %trunc6 = trunc i32 %val6 to i8147 %trunc7 = trunc i32 %val7 to i8148 %trunc8 = trunc i32 %val8 to i8149 %trunc9 = trunc i32 %val9 to i8150 %trunc10 = trunc i32 %val10 to i8151 %trunc11 = trunc i32 %val11 to i8152 %trunc12 = trunc i32 %val12 to i8153 %trunc13 = trunc i32 %val13 to i8154 %trunc14 = trunc i32 %val14 to i8155 %trunc15 = trunc i32 %val15 to i8156 157 %ext0 = zext i8 %trunc0 to i32158 %ext1 = zext i8 %trunc1 to i32159 %ext2 = zext i8 %trunc2 to i32160 %ext3 = zext i8 %trunc3 to i32161 %ext4 = zext i8 %trunc4 to i32162 %ext5 = zext i8 %trunc5 to i32163 %ext6 = zext i8 %trunc6 to i32164 %ext7 = zext i8 %trunc7 to i32165 %ext8 = zext i8 %trunc8 to i32166 %ext9 = zext i8 %trunc9 to i32167 %ext10 = zext i8 %trunc10 to i32168 %ext11 = zext i8 %trunc11 to i32169 %ext12 = zext i8 %trunc12 to i32170 %ext13 = zext i8 %trunc13 to i32171 %ext14 = zext i8 %trunc14 to i32172 %ext15 = zext i8 %trunc15 to i32173 174 store volatile i32 %val0, ptr %ptr175 store volatile i32 %val1, ptr %ptr176 store volatile i32 %val2, ptr %ptr177 store volatile i32 %val3, ptr %ptr178 store volatile i32 %val4, ptr %ptr179 store volatile i32 %val5, ptr %ptr180 store volatile i32 %val6, ptr %ptr181 store volatile i32 %val7, ptr %ptr182 store volatile i32 %val8, ptr %ptr183 store volatile i32 %val9, ptr %ptr184 store volatile i32 %val10, ptr %ptr185 store volatile i32 %val11, ptr %ptr186 store volatile i32 %val12, ptr %ptr187 store volatile i32 %val13, ptr %ptr188 store volatile i32 %val14, ptr %ptr189 store volatile i32 %val15, ptr %ptr190 191 store volatile i32 %ext0, ptr %ptr192 store volatile i32 %ext1, ptr %ptr193 store volatile i32 %ext2, ptr %ptr194 store volatile i32 %ext3, ptr %ptr195 store volatile i32 %ext4, ptr %ptr196 store volatile i32 %ext5, ptr %ptr197 store volatile i32 %ext6, ptr %ptr198 store volatile i32 %ext7, ptr %ptr199 store volatile i32 %ext8, ptr %ptr200 store volatile i32 %ext9, ptr %ptr201 store volatile i32 %ext10, ptr %ptr202 store volatile i32 %ext11, ptr %ptr203 store volatile i32 %ext12, ptr %ptr204 store volatile i32 %ext13, ptr %ptr205 store volatile i32 %ext14, ptr %ptr206 store volatile i32 %ext15, ptr %ptr207 208 ret void209}210