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1; Test zero extensions from an i32 to an i64.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5; Test register extension, starting with an i32.6define i64 @f1(i32 %a) {7; CHECK-LABEL: f1:8; CHECK: llgfr %r2, %r29; CHECK: br %r1410 %ext = zext i32 %a to i6411 ret i64 %ext12}13 14; ...and again with an i64.15define i64 @f2(i64 %a) {16; CHECK-LABEL: f2:17; CHECK: llgfr %r2, %r218; CHECK: br %r1419 %word = trunc i64 %a to i3220 %ext = zext i32 %word to i6421 ret i64 %ext22}23 24; Check ANDs that are equivalent to zero extension.25define i64 @f3(i64 %a) {26; CHECK-LABEL: f3:27; CHECK: llgfr %r2, %r228; CHECK: br %r1429 %ext = and i64 %a, 429496729530 ret i64 %ext31}32 33; Check LLGF with no displacement.34define i64 @f4(ptr %src) {35; CHECK-LABEL: f4:36; CHECK: llgf %r2, 0(%r2)37; CHECK: br %r1438 %word = load i32, ptr %src39 %ext = zext i32 %word to i6440 ret i64 %ext41}42 43; Check the high end of the LLGF range.44define i64 @f5(ptr %src) {45; CHECK-LABEL: f5:46; CHECK: llgf %r2, 524284(%r2)47; CHECK: br %r1448 %ptr = getelementptr i32, ptr %src, i64 13107149 %word = load i32, ptr %ptr50 %ext = zext i32 %word to i6451 ret i64 %ext52}53 54; Check the next word up, which needs separate address logic.55; Other sequences besides this one would be OK.56define i64 @f6(ptr %src) {57; CHECK-LABEL: f6:58; CHECK: agfi %r2, 52428859; CHECK: llgf %r2, 0(%r2)60; CHECK: br %r1461 %ptr = getelementptr i32, ptr %src, i64 13107262 %word = load i32, ptr %ptr63 %ext = zext i32 %word to i6464 ret i64 %ext65}66 67; Check the high end of the negative LLGF range.68define i64 @f7(ptr %src) {69; CHECK-LABEL: f7:70; CHECK: llgf %r2, -4(%r2)71; CHECK: br %r1472 %ptr = getelementptr i32, ptr %src, i64 -173 %word = load i32, ptr %ptr74 %ext = zext i32 %word to i6475 ret i64 %ext76}77 78; Check the low end of the LLGF range.79define i64 @f8(ptr %src) {80; CHECK-LABEL: f8:81; CHECK: llgf %r2, -524288(%r2)82; CHECK: br %r1483 %ptr = getelementptr i32, ptr %src, i64 -13107284 %word = load i32, ptr %ptr85 %ext = zext i32 %word to i6486 ret i64 %ext87}88 89; Check the next word down, which needs separate address logic.90; Other sequences besides this one would be OK.91define i64 @f9(ptr %src) {92; CHECK-LABEL: f9:93; CHECK: agfi %r2, -52429294; CHECK: llgf %r2, 0(%r2)95; CHECK: br %r1496 %ptr = getelementptr i32, ptr %src, i64 -13107397 %word = load i32, ptr %ptr98 %ext = zext i32 %word to i6499 ret i64 %ext100}101 102; Check that LLGF allows an index.103define i64 @f10(i64 %src, i64 %index) {104; CHECK-LABEL: f10:105; CHECK: llgf %r2, 524287(%r3,%r2)106; CHECK: br %r14107 %add1 = add i64 %src, %index108 %add2 = add i64 %add1, 524287109 %ptr = inttoptr i64 %add2 to ptr110 %word = load i32, ptr %ptr111 %ext = zext i32 %word to i64112 ret i64 %ext113}114