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1; Test 31-to-64 bit zero extensions.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5; Test register extension, starting with an i64.6define i64 @f1(i64 %a) {7; CHECK-LABEL: f1:8; CHECK: llgtr %r2, %r29; CHECK: br %r1410 %ext = and i64 %a, 214748364711 ret i64 %ext12}13 14; Test register extension, starting with an i32.15define i64 @f2(i32 %a) {16; CHECK-LABEL: f2:17; CHECK: llgtr %r2, %r218; CHECK: br %r1419 %and = and i32 %a, 214748364720 %ext = zext i32 %and to i6421 ret i64 %ext22}23 24; ... and the other way around.25define i64 @f3(i32 %a) {26; CHECK-LABEL: f3:27; CHECK: llgtr %r2, %r228; CHECK: br %r1429 %ext = zext i32 %a to i6430 %and = and i64 %ext, 214748364731 ret i64 %and32}33 34; Check LLGT with no displacement.35define i64 @f4(ptr %src) {36; CHECK-LABEL: f4:37; CHECK: llgt %r2, 0(%r2)38; CHECK: br %r1439 %word = load i32, ptr %src40 %ext = zext i32 %word to i6441 %and = and i64 %ext, 214748364742 ret i64 %and43}44 45; ... and the other way around.46define i64 @f5(ptr %src) {47; CHECK-LABEL: f5:48; CHECK: llgt %r2, 0(%r2)49; CHECK: br %r1450 %word = load i32, ptr %src51 %and = and i32 %word, 214748364752 %ext = zext i32 %and to i6453 ret i64 %ext54}55 56; Check the high end of the LLGT range.57define i64 @f6(ptr %src) {58; CHECK-LABEL: f6:59; CHECK: llgt %r2, 524284(%r2)60; CHECK: br %r1461 %ptr = getelementptr i32, ptr %src, i64 13107162 %word = load i32, ptr %ptr63 %ext = zext i32 %word to i6464 %and = and i64 %ext, 214748364765 ret i64 %and66}67 68; Check the next word up, which needs separate address logic.69; Other sequences besides this one would be OK.70define i64 @f7(ptr %src) {71; CHECK-LABEL: f7:72; CHECK: agfi %r2, 52428873; CHECK: llgt %r2, 0(%r2)74; CHECK: br %r1475 %ptr = getelementptr i32, ptr %src, i64 13107276 %word = load i32, ptr %ptr77 %ext = zext i32 %word to i6478 %and = and i64 %ext, 214748364779 ret i64 %and80}81 82; Check the high end of the negative LLGT range.83define i64 @f8(ptr %src) {84; CHECK-LABEL: f8:85; CHECK: llgt %r2, -4(%r2)86; CHECK: br %r1487 %ptr = getelementptr i32, ptr %src, i64 -188 %word = load i32, ptr %ptr89 %ext = zext i32 %word to i6490 %and = and i64 %ext, 214748364791 ret i64 %and92}93 94; Check the low end of the LLGT range.95define i64 @f9(ptr %src) {96; CHECK-LABEL: f9:97; CHECK: llgt %r2, -524288(%r2)98; CHECK: br %r1499 %ptr = getelementptr i32, ptr %src, i64 -131072100 %word = load i32, ptr %ptr101 %ext = zext i32 %word to i64102 %and = and i64 %ext, 2147483647103 ret i64 %and104}105 106; Check the next word down, which needs separate address logic.107; Other sequences besides this one would be OK.108define i64 @f10(ptr %src) {109; CHECK-LABEL: f10:110; CHECK: agfi %r2, -524292111; CHECK: llgt %r2, 0(%r2)112; CHECK: br %r14113 %ptr = getelementptr i32, ptr %src, i64 -131073114 %word = load i32, ptr %ptr115 %ext = zext i32 %word to i64116 %and = and i64 %ext, 2147483647117 ret i64 %and118}119 120; Check that LLGT allows an index.121define i64 @f11(i64 %src, i64 %index) {122; CHECK-LABEL: f11:123; CHECK: llgt %r2, 524287(%r3,%r2)124; CHECK: br %r14125 %add1 = add i64 %src, %index126 %add2 = add i64 %add1, 524287127 %ptr = inttoptr i64 %add2 to ptr128 %word = load i32, ptr %ptr129 %ext = zext i32 %word to i64130 %and = and i64 %ext, 2147483647131 ret i64 %and132}133 134