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1; Test load and zero rightmost byte.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Check LZRF with no displacement.6define i32 @f1(ptr %src) {7; CHECK-LABEL: f1:8; CHECK: lzrf %r2, 0(%r2)9; CHECK: br %r1410 %val = load i32, ptr %src11 %and = and i32 %val, 429496704012 ret i32 %and13}14 15; Check the high end of the LZRF range.16define i32 @f2(ptr %src) {17; CHECK-LABEL: f2:18; CHECK: lzrf %r2, 524284(%r2)19; CHECK: br %r1420 %ptr = getelementptr i32, ptr %src, i64 13107121 %val = load i32, ptr %ptr22 %and = and i32 %val, 429496704023 ret i32 %and24}25 26; Check the next word up, which needs separate address logic.27; Other sequences besides this one would be OK.28define i32 @f3(ptr %src) {29; CHECK-LABEL: f3:30; CHECK: agfi %r2, 52428831; CHECK: lzrf %r2, 0(%r2)32; CHECK: br %r1433 %ptr = getelementptr i32, ptr %src, i64 13107234 %val = load i32, ptr %ptr35 %and = and i32 %val, 429496704036 ret i32 %and37}38 39; Check the high end of the negative LZRF range.40define i32 @f4(ptr %src) {41; CHECK-LABEL: f4:42; CHECK: lzrf %r2, -4(%r2)43; CHECK: br %r1444 %ptr = getelementptr i32, ptr %src, i64 -145 %val = load i32, ptr %ptr46 %and = and i32 %val, 429496704047 ret i32 %and48}49 50; Check the low end of the LZRF range.51define i32 @f5(ptr %src) {52; CHECK-LABEL: f5:53; CHECK: lzrf %r2, -524288(%r2)54; CHECK: br %r1455 %ptr = getelementptr i32, ptr %src, i64 -13107256 %val = load i32, ptr %ptr57 %and = and i32 %val, 429496704058 ret i32 %and59}60 61; Check the next word down, which needs separate address logic.62; Other sequences besides this one would be OK.63define i32 @f6(ptr %src) {64; CHECK-LABEL: f6:65; CHECK: agfi %r2, -52429266; CHECK: lzrf %r2, 0(%r2)67; CHECK: br %r1468 %ptr = getelementptr i32, ptr %src, i64 -13107369 %val = load i32, ptr %ptr70 %and = and i32 %val, 429496704071 ret i32 %and72}73 74; Check that LZRF allows an index.75define i32 @f7(i64 %src, i64 %index) {76; CHECK-LABEL: f7:77; CHECK: lzrf %r2, 524287(%r3,%r2)78; CHECK: br %r1479 %add1 = add i64 %src, %index80 %add2 = add i64 %add1, 52428781 %ptr = inttoptr i64 %add2 to ptr82 %val = load i32, ptr %ptr83 %and = and i32 %val, 429496704084 ret i32 %and85}86 87; Check LZRG with no displacement.88define i64 @f8(ptr %src) {89; CHECK-LABEL: f8:90; CHECK: lzrg %r2, 0(%r2)91; CHECK: br %r1492 %val = load i64, ptr %src93 %and = and i64 %val, 1844674407370955136094 ret i64 %and95}96 97; Check the high end of the LZRG range.98define i64 @f9(ptr %src) {99; CHECK-LABEL: f9:100; CHECK: lzrg %r2, 524280(%r2)101; CHECK: br %r14102 %ptr = getelementptr i64, ptr %src, i64 65535103 %val = load i64, ptr %ptr104 %and = and i64 %val, 18446744073709551360105 ret i64 %and106}107 108; Check the next word up, which needs separate address logic.109; Other sequences besides this one would be OK.110define i64 @f10(ptr %src) {111; CHECK-LABEL: f10:112; CHECK: agfi %r2, 524288113; CHECK: lzrg %r2, 0(%r2)114; CHECK: br %r14115 %ptr = getelementptr i64, ptr %src, i64 65536116 %val = load i64, ptr %ptr117 %and = and i64 %val, 18446744073709551360118 ret i64 %and119}120 121; Check the high end of the negative LZRG range.122define i64 @f11(ptr %src) {123; CHECK-LABEL: f11:124; CHECK: lzrg %r2, -8(%r2)125; CHECK: br %r14126 %ptr = getelementptr i64, ptr %src, i64 -1127 %val = load i64, ptr %ptr128 %and = and i64 %val, 18446744073709551360129 ret i64 %and130}131 132; Check the low end of the LZRG range.133define i64 @f12(ptr %src) {134; CHECK-LABEL: f12:135; CHECK: lzrg %r2, -524288(%r2)136; CHECK: br %r14137 %ptr = getelementptr i64, ptr %src, i64 -65536138 %val = load i64, ptr %ptr139 %and = and i64 %val, 18446744073709551360140 ret i64 %and141}142 143; Check the next word down, which needs separate address logic.144; Other sequences besides this one would be OK.145define i64 @f13(ptr %src) {146; CHECK-LABEL: f13:147; CHECK: agfi %r2, -524296148; CHECK: lzrg %r2, 0(%r2)149; CHECK: br %r14150 %ptr = getelementptr i64, ptr %src, i64 -65537151 %val = load i64, ptr %ptr152 %and = and i64 %val, 18446744073709551360153 ret i64 %and154}155 156; Check that LZRG allows an index.157define i64 @f14(i64 %src, i64 %index) {158; CHECK-LABEL: f14:159; CHECK: lzrg %r2, 524287(%r3,%r2)160; CHECK: br %r14161 %add1 = add i64 %src, %index162 %add2 = add i64 %add1, 524287163 %ptr = inttoptr i64 %add2 to ptr164 %val = load i64, ptr %ptr165 %and = and i64 %val, 18446744073709551360166 ret i64 %and167}168 169; Check LLZRGF with no displacement.170define i64 @f15(ptr %src) {171; CHECK-LABEL: f15:172; CHECK: llzrgf %r2, 0(%r2)173; CHECK: br %r14174 %val = load i32, ptr %src175 %ext = zext i32 %val to i64176 %and = and i64 %ext, 18446744073709551360177 ret i64 %and178}179 180; ... and the other way around.181define i64 @f16(ptr %src) {182; CHECK-LABEL: f16:183; CHECK: llzrgf %r2, 0(%r2)184; CHECK: br %r14185 %val = load i32, ptr %src186 %and = and i32 %val, 4294967040187 %ext = zext i32 %and to i64188 ret i64 %ext189}190 191; Check the high end of the LLZRGF range.192define i64 @f17(ptr %src) {193; CHECK-LABEL: f17:194; CHECK: llzrgf %r2, 524284(%r2)195; CHECK: br %r14196 %ptr = getelementptr i32, ptr %src, i64 131071197 %val = load i32, ptr %ptr198 %and = and i32 %val, 4294967040199 %ext = zext i32 %and to i64200 ret i64 %ext201}202 203; Check the next word up, which needs separate address logic.204; Other sequences besides this one would be OK.205define i64 @f18(ptr %src) {206; CHECK-LABEL: f18:207; CHECK: agfi %r2, 524288208; CHECK: llzrgf %r2, 0(%r2)209; CHECK: br %r14210 %ptr = getelementptr i32, ptr %src, i64 131072211 %val = load i32, ptr %ptr212 %and = and i32 %val, 4294967040213 %ext = zext i32 %and to i64214 ret i64 %ext215}216 217; Check the high end of the negative LLZRGF range.218define i64 @f19(ptr %src) {219; CHECK-LABEL: f19:220; CHECK: llzrgf %r2, -4(%r2)221; CHECK: br %r14222 %ptr = getelementptr i32, ptr %src, i64 -1223 %val = load i32, ptr %ptr224 %and = and i32 %val, 4294967040225 %ext = zext i32 %and to i64226 ret i64 %ext227}228 229; Check the low end of the LLZRGF range.230define i64 @f20(ptr %src) {231; CHECK-LABEL: f20:232; CHECK: llzrgf %r2, -524288(%r2)233; CHECK: br %r14234 %ptr = getelementptr i32, ptr %src, i64 -131072235 %val = load i32, ptr %ptr236 %and = and i32 %val, 4294967040237 %ext = zext i32 %and to i64238 ret i64 %ext239}240 241; Check the next word down, which needs separate address logic.242; Other sequences besides this one would be OK.243define i64 @f21(ptr %src) {244; CHECK-LABEL: f21:245; CHECK: agfi %r2, -524292246; CHECK: llzrgf %r2, 0(%r2)247; CHECK: br %r14248 %ptr = getelementptr i32, ptr %src, i64 -131073249 %val = load i32, ptr %ptr250 %and = and i32 %val, 4294967040251 %ext = zext i32 %and to i64252 ret i64 %ext253}254 255; Check that LLZRGF allows an index.256define i64 @f22(i64 %src, i64 %index) {257; CHECK-LABEL: f22:258; CHECK: llzrgf %r2, 524287(%r3,%r2)259; CHECK: br %r14260 %add1 = add i64 %src, %index261 %add2 = add i64 %add1, 524287262 %ptr = inttoptr i64 %add2 to ptr263 %val = load i32, ptr %ptr264 %and = and i32 %val, 4294967040265 %ext = zext i32 %and to i64266 ret i64 %ext267}268 269; Check that we still get a RISBGN if the source is in a register.270define i64 @f23(i32 %src) {271; CHECK-LABEL: f23:272; CHECK: risbgn %r2, %r2, 32, 183, 0273; CHECK: br %r14274 %and = and i32 %src, 4294967040275 %ext = zext i32 %and to i64276 ret i64 %ext277}278 279