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1; Test 32-bit unsigned division and remainder.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s4 5declare i32 @foo()6 7; Test register division. The result is in the second of the two registers.8define void @f1(i32 %dummy, i32 %a, i32 %b, ptr %dest) {9; CHECK-LABEL: f1:10; CHECK-NOT: %r311; CHECK: {{llill|lhi}} %r2, 012; CHECK-NOT: %r313; CHECK: dlr %r2, %r414; CHECK: st %r3, 0(%r5)15; CHECK: br %r1416 %div = udiv i32 %a, %b17 store i32 %div, ptr %dest18 ret void19}20 21; Test register remainder. The result is in the first of the two registers.22define void @f2(i32 %dummy, i32 %a, i32 %b, ptr %dest) {23; CHECK-LABEL: f2:24; CHECK-NOT: %r325; CHECK: {{llill|lhi}} %r2, 026; CHECK-NOT: %r327; CHECK: dlr %r2, %r428; CHECK: st %r2, 0(%r5)29; CHECK: br %r1430 %rem = urem i32 %a, %b31 store i32 %rem, ptr %dest32 ret void33}34 35; Test that division and remainder use a single instruction.36define i32 @f3(i32 %dummy1, i32 %a, i32 %b) {37; CHECK-LABEL: f3:38; CHECK-NOT: %r339; CHECK: {{llill|lhi}} %r2, 040; CHECK-NOT: %r341; CHECK: dlr %r2, %r442; CHECK-NOT: dlr43; CHECK: or %r2, %r344; CHECK: br %r1445 %div = udiv i32 %a, %b46 %rem = urem i32 %a, %b47 %or = or i32 %rem, %div48 ret i32 %or49}50 51; Test memory division with no displacement.52define void @f4(i32 %dummy, i32 %a, ptr %src, ptr %dest) {53; CHECK-LABEL: f4:54; CHECK-NOT: %r355; CHECK: {{llill|lhi}} %r2, 056; CHECK-NOT: %r357; CHECK: dl %r2, 0(%r4)58; CHECK: st %r3, 0(%r5)59; CHECK: br %r1460 %b = load i32, ptr %src61 %div = udiv i32 %a, %b62 store i32 %div, ptr %dest63 ret void64}65 66; Test memory remainder with no displacement.67define void @f5(i32 %dummy, i32 %a, ptr %src, ptr %dest) {68; CHECK-LABEL: f5:69; CHECK-NOT: %r370; CHECK: {{llill|lhi}} %r2, 071; CHECK-NOT: %r372; CHECK: dl %r2, 0(%r4)73; CHECK: st %r2, 0(%r5)74; CHECK: br %r1475 %b = load i32, ptr %src76 %rem = urem i32 %a, %b77 store i32 %rem, ptr %dest78 ret void79}80 81; Test both memory division and memory remainder.82define i32 @f6(i32 %dummy, i32 %a, ptr %src) {83; CHECK-LABEL: f6:84; CHECK-NOT: %r385; CHECK: {{llill|lhi}} %r2, 086; CHECK-NOT: %r387; CHECK: dl %r2, 0(%r4)88; CHECK-NOT: {{dl|dlr}}89; CHECK: or %r2, %r390; CHECK: br %r1491 %b = load i32, ptr %src92 %div = udiv i32 %a, %b93 %rem = urem i32 %a, %b94 %or = or i32 %rem, %div95 ret i32 %or96}97 98; Check the high end of the DL range.99define i32 @f7(i32 %dummy, i32 %a, ptr %src) {100; CHECK-LABEL: f7:101; CHECK: dl %r2, 524284(%r4)102; CHECK: br %r14103 %ptr = getelementptr i32, ptr %src, i64 131071104 %b = load i32, ptr %ptr105 %rem = urem i32 %a, %b106 ret i32 %rem107}108 109; Check the next word up, which needs separate address logic.110; Other sequences besides this one would be OK.111define i32 @f8(i32 %dummy, i32 %a, ptr %src) {112; CHECK-LABEL: f8:113; CHECK: agfi %r4, 524288114; CHECK: dl %r2, 0(%r4)115; CHECK: br %r14116 %ptr = getelementptr i32, ptr %src, i64 131072117 %b = load i32, ptr %ptr118 %rem = urem i32 %a, %b119 ret i32 %rem120}121 122; Check the high end of the negative aligned DL range.123define i32 @f9(i32 %dummy, i32 %a, ptr %src) {124; CHECK-LABEL: f9:125; CHECK: dl %r2, -4(%r4)126; CHECK: br %r14127 %ptr = getelementptr i32, ptr %src, i64 -1128 %b = load i32, ptr %ptr129 %rem = urem i32 %a, %b130 ret i32 %rem131}132 133; Check the low end of the DL range.134define i32 @f10(i32 %dummy, i32 %a, ptr %src) {135; CHECK-LABEL: f10:136; CHECK: dl %r2, -524288(%r4)137; CHECK: br %r14138 %ptr = getelementptr i32, ptr %src, i64 -131072139 %b = load i32, ptr %ptr140 %rem = urem i32 %a, %b141 ret i32 %rem142}143 144; Check the next word down, which needs separate address logic.145; Other sequences besides this one would be OK.146define i32 @f11(i32 %dummy, i32 %a, ptr %src) {147; CHECK-LABEL: f11:148; CHECK: agfi %r4, -524292149; CHECK: dl %r2, 0(%r4)150; CHECK: br %r14151 %ptr = getelementptr i32, ptr %src, i64 -131073152 %b = load i32, ptr %ptr153 %rem = urem i32 %a, %b154 ret i32 %rem155}156 157; Check that DL allows an index.158define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {159; CHECK-LABEL: f12:160; CHECK: dl %r2, 524287(%r5,%r4)161; CHECK: br %r14162 %add1 = add i64 %src, %index163 %add2 = add i64 %add1, 524287164 %ptr = inttoptr i64 %add2 to ptr165 %b = load i32, ptr %ptr166 %rem = urem i32 %a, %b167 ret i32 %rem168}169 170; Check that divisions of spilled values can use DL rather than DLR.171define i32 @f13(ptr %ptr0) {172; CHECK-LABEL: f13:173; CHECK: brasl %r14, foo@PLT174; CHECK: dl {{%r[0-9]+}}, 16{{[04]}}(%r15)175; CHECK: br %r14176 %ptr1 = getelementptr i32, ptr %ptr0, i64 2177 %ptr2 = getelementptr i32, ptr %ptr0, i64 4178 %ptr3 = getelementptr i32, ptr %ptr0, i64 6179 %ptr4 = getelementptr i32, ptr %ptr0, i64 8180 %ptr5 = getelementptr i32, ptr %ptr0, i64 10181 %ptr6 = getelementptr i32, ptr %ptr0, i64 12182 %ptr7 = getelementptr i32, ptr %ptr0, i64 14183 %ptr8 = getelementptr i32, ptr %ptr0, i64 16184 %ptr9 = getelementptr i32, ptr %ptr0, i64 18185 186 %val0 = load i32, ptr %ptr0187 %val1 = load i32, ptr %ptr1188 %val2 = load i32, ptr %ptr2189 %val3 = load i32, ptr %ptr3190 %val4 = load i32, ptr %ptr4191 %val5 = load i32, ptr %ptr5192 %val6 = load i32, ptr %ptr6193 %val7 = load i32, ptr %ptr7194 %val8 = load i32, ptr %ptr8195 %val9 = load i32, ptr %ptr9196 197 %ret = call i32 @foo()198 199 %div0 = udiv i32 %ret, %val0200 %div1 = udiv i32 %div0, %val1201 %div2 = udiv i32 %div1, %val2202 %div3 = udiv i32 %div2, %val3203 %div4 = udiv i32 %div3, %val4204 %div5 = udiv i32 %div4, %val5205 %div6 = udiv i32 %div5, %val6206 %div7 = udiv i32 %div6, %val7207 %div8 = udiv i32 %div7, %val8208 %div9 = udiv i32 %div8, %val9209 210 ret i32 %div9211}212