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1; Testg 64-bit unsigned division and remainder.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s4 5declare i64 @foo()6 7; Testg register division. The result is in the second of the two registers.8define void @f1(i64 %dummy, i64 %a, i64 %b, ptr %dest) {9; CHECK-LABEL: f1:10; CHECK-NOT: %r311; CHECK: {{llill|lghi}} %r2, 012; CHECK-NOT: %r313; CHECK: dlgr %r2, %r414; CHECK: stg %r3, 0(%r5)15; CHECK: br %r1416 %div = udiv i64 %a, %b17 store i64 %div, ptr %dest18 ret void19}20 21; Testg register remainder. The result is in the first of the two registers.22define void @f2(i64 %dummy, i64 %a, i64 %b, ptr %dest) {23; CHECK-LABEL: f2:24; CHECK-NOT: %r325; CHECK: {{llill|lghi}} %r2, 026; CHECK-NOT: %r327; CHECK: dlgr %r2, %r428; CHECK: stg %r2, 0(%r5)29; CHECK: br %r1430 %rem = urem i64 %a, %b31 store i64 %rem, ptr %dest32 ret void33}34 35; Testg that division and remainder use a single instruction.36define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {37; CHECK-LABEL: f3:38; CHECK-NOT: %r339; CHECK: {{llill|lghi}} %r2, 040; CHECK-NOT: %r341; CHECK: dlgr %r2, %r442; CHECK-NOT: dlgr43; CHECK: ogr %r2, %r344; CHECK: br %r1445 %div = udiv i64 %a, %b46 %rem = urem i64 %a, %b47 %or = or i64 %rem, %div48 ret i64 %or49}50 51; Testg memory division with no displacement.52define void @f4(i64 %dummy, i64 %a, ptr %src, ptr %dest) {53; CHECK-LABEL: f4:54; CHECK-NOT: %r355; CHECK: {{llill|lghi}} %r2, 056; CHECK-NOT: %r357; CHECK: dlg %r2, 0(%r4)58; CHECK: stg %r3, 0(%r5)59; CHECK: br %r1460 %b = load i64, ptr %src61 %div = udiv i64 %a, %b62 store i64 %div, ptr %dest63 ret void64}65 66; Testg memory remainder with no displacement.67define void @f5(i64 %dummy, i64 %a, ptr %src, ptr %dest) {68; CHECK-LABEL: f5:69; CHECK-NOT: %r370; CHECK: {{llill|lghi}} %r2, 071; CHECK-NOT: %r372; CHECK: dlg %r2, 0(%r4)73; CHECK: stg %r2, 0(%r5)74; CHECK: br %r1475 %b = load i64, ptr %src76 %rem = urem i64 %a, %b77 store i64 %rem, ptr %dest78 ret void79}80 81; Testg both memory division and memory remainder.82define i64 @f6(i64 %dummy, i64 %a, ptr %src) {83; CHECK-LABEL: f6:84; CHECK-NOT: %r385; CHECK: {{llill|lghi}} %r2, 086; CHECK-NOT: %r387; CHECK: dlg %r2, 0(%r4)88; CHECK-NOT: {{dlg|dlgr}}89; CHECK: ogr %r2, %r390; CHECK: br %r1491 %b = load i64, ptr %src92 %div = udiv i64 %a, %b93 %rem = urem i64 %a, %b94 %or = or i64 %rem, %div95 ret i64 %or96}97 98; Check the high end of the DLG range.99define i64 @f7(i64 %dummy, i64 %a, ptr %src) {100; CHECK-LABEL: f7:101; CHECK: dlg %r2, 524280(%r4)102; CHECK: br %r14103 %ptr = getelementptr i64, ptr %src, i64 65535104 %b = load i64, ptr %ptr105 %rem = urem i64 %a, %b106 ret i64 %rem107}108 109; Check the next doubleword up, which needs separate address logic.110; Other sequences besides this one would be OK.111define i64 @f8(i64 %dummy, i64 %a, ptr %src) {112; CHECK-LABEL: f8:113; CHECK: agfi %r4, 524288114; CHECK: dlg %r2, 0(%r4)115; CHECK: br %r14116 %ptr = getelementptr i64, ptr %src, i64 65536117 %b = load i64, ptr %ptr118 %rem = urem i64 %a, %b119 ret i64 %rem120}121 122; Check the high end of the negative aligned DLG range.123define i64 @f9(i64 %dummy, i64 %a, ptr %src) {124; CHECK-LABEL: f9:125; CHECK: dlg %r2, -8(%r4)126; CHECK: br %r14127 %ptr = getelementptr i64, ptr %src, i64 -1128 %b = load i64, ptr %ptr129 %rem = urem i64 %a, %b130 ret i64 %rem131}132 133; Check the low end of the DLG range.134define i64 @f10(i64 %dummy, i64 %a, ptr %src) {135; CHECK-LABEL: f10:136; CHECK: dlg %r2, -524288(%r4)137; CHECK: br %r14138 %ptr = getelementptr i64, ptr %src, i64 -65536139 %b = load i64, ptr %ptr140 %rem = urem i64 %a, %b141 ret i64 %rem142}143 144; Check the next doubleword down, which needs separate address logic.145; Other sequences besides this one would be OK.146define i64 @f11(i64 %dummy, i64 %a, ptr %src) {147; CHECK-LABEL: f11:148; CHECK: agfi %r4, -524296149; CHECK: dlg %r2, 0(%r4)150; CHECK: br %r14151 %ptr = getelementptr i64, ptr %src, i64 -65537152 %b = load i64, ptr %ptr153 %rem = urem i64 %a, %b154 ret i64 %rem155}156 157; Check that DLG allows an index.158define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {159; CHECK-LABEL: f12:160; CHECK: dlg %r2, 524287(%r5,%r4)161; CHECK: br %r14162 %add1 = add i64 %src, %index163 %add2 = add i64 %add1, 524287164 %ptr = inttoptr i64 %add2 to ptr165 %b = load i64, ptr %ptr166 %rem = urem i64 %a, %b167 ret i64 %rem168}169 170; Check that divisions of spilled values can use DLG rather than DLGR.171define i64 @f13(ptr %ptr0) {172; CHECK-LABEL: f13:173; CHECK: brasl %r14, foo@PLT174; CHECK: dlg {{%r[0-9]+}}, 160(%r15)175; CHECK: br %r14176 %ptr1 = getelementptr i64, ptr %ptr0, i64 2177 %ptr2 = getelementptr i64, ptr %ptr0, i64 4178 %ptr3 = getelementptr i64, ptr %ptr0, i64 6179 %ptr4 = getelementptr i64, ptr %ptr0, i64 8180 %ptr5 = getelementptr i64, ptr %ptr0, i64 10181 %ptr6 = getelementptr i64, ptr %ptr0, i64 12182 %ptr7 = getelementptr i64, ptr %ptr0, i64 14183 %ptr8 = getelementptr i64, ptr %ptr0, i64 16184 %ptr9 = getelementptr i64, ptr %ptr0, i64 18185 %ptr10 = getelementptr i64, ptr %ptr0, i64 20186 187 %val0 = load i64, ptr %ptr0188 %val1 = load i64, ptr %ptr1189 %val2 = load i64, ptr %ptr2190 %val3 = load i64, ptr %ptr3191 %val4 = load i64, ptr %ptr4192 %val5 = load i64, ptr %ptr5193 %val6 = load i64, ptr %ptr6194 %val7 = load i64, ptr %ptr7195 %val8 = load i64, ptr %ptr8196 %val9 = load i64, ptr %ptr9197 %val10 = load i64, ptr %ptr10198 199 %ret = call i64 @foo()200 201 %div0 = udiv i64 %ret, %val0202 %div1 = udiv i64 %div0, %val1203 %div2 = udiv i64 %div1, %val2204 %div3 = udiv i64 %div2, %val3205 %div4 = udiv i64 %div3, %val4206 %div5 = udiv i64 %div4, %val5207 %div6 = udiv i64 %div5, %val6208 %div7 = udiv i64 %div6, %val7209 %div8 = udiv i64 %div7, %val8210 %div9 = udiv i64 %div8, %val9211 %div10 = udiv i64 %div9, %val10212 213 ret i64 %div10214}215