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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test 128-bit division and remainder in vector registers on z173;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s5 6; Divide signed.7define i128 @f1(i128 %a, i128 %b) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl %v0, 0(%r4), 311; CHECK-NEXT: vl %v1, 0(%r3), 312; CHECK-NEXT: vdq %v0, %v1, %v0, 013; CHECK-NEXT: vst %v0, 0(%r2), 314; CHECK-NEXT: br %r1415 %res = sdiv i128 %a, %b16 ret i128 %res17}18 19; Divide unsigned.20define i128 @f2(i128 %a, i128 %b) {21; CHECK-LABEL: f2:22; CHECK: # %bb.0:23; CHECK-NEXT: vl %v0, 0(%r4), 324; CHECK-NEXT: vl %v1, 0(%r3), 325; CHECK-NEXT: vdlq %v0, %v1, %v0, 026; CHECK-NEXT: vst %v0, 0(%r2), 327; CHECK-NEXT: br %r1428 %res = udiv i128 %a, %b29 ret i128 %res30}31 32; Remainder signed.33define i128 @f3(i128 %a, i128 %b) {34; CHECK-LABEL: f3:35; CHECK: # %bb.0:36; CHECK-NEXT: vl %v0, 0(%r4), 337; CHECK-NEXT: vl %v1, 0(%r3), 338; CHECK-NEXT: vrq %v0, %v1, %v0, 039; CHECK-NEXT: vst %v0, 0(%r2), 340; CHECK-NEXT: br %r1441 %res = srem i128 %a, %b42 ret i128 %res43}44 45; Remainder unsigned.46define i128 @f4(i128 %a, i128 %b) {47; CHECK-LABEL: f4:48; CHECK: # %bb.0:49; CHECK-NEXT: vl %v0, 0(%r4), 350; CHECK-NEXT: vl %v1, 0(%r3), 351; CHECK-NEXT: vrlq %v0, %v1, %v0, 052; CHECK-NEXT: vst %v0, 0(%r2), 353; CHECK-NEXT: br %r1454 %res = urem i128 %a, %b55 ret i128 %res56}57