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1; Test 16-bit GPR stores.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5; Test an i16 store, which should get converted into an i32 truncation.6define void @f1(ptr %dst, i16 %val) {7; CHECK-LABEL: f1:8; CHECK: sth %r3, 0(%r2)9; CHECK: br %r1410 store i16 %val, ptr %dst11 ret void12}13 14; Test an i32 truncating store.15define void @f2(ptr %dst, i32 %val) {16; CHECK-LABEL: f2:17; CHECK: sth %r3, 0(%r2)18; CHECK: br %r1419 %trunc = trunc i32 %val to i1620 store i16 %trunc, ptr %dst21 ret void22}23 24; Test an i64 truncating store.25define void @f3(ptr %dst, i64 %val) {26; CHECK-LABEL: f3:27; CHECK: sth %r3, 0(%r2)28; CHECK: br %r1429 %trunc = trunc i64 %val to i1630 store i16 %trunc, ptr %dst31 ret void32}33 34; Check the high end of the STH range.35define void @f4(ptr %dst, i16 %val) {36; CHECK-LABEL: f4:37; CHECK: sth %r3, 4094(%r2)38; CHECK: br %r1439 %ptr = getelementptr i16, ptr %dst, i64 204740 store i16 %val, ptr %ptr41 ret void42}43 44; Check the next halfword up, which should use STHY instead of STH.45define void @f5(ptr %dst, i16 %val) {46; CHECK-LABEL: f5:47; CHECK: sthy %r3, 4096(%r2)48; CHECK: br %r1449 %ptr = getelementptr i16, ptr %dst, i64 204850 store i16 %val, ptr %ptr51 ret void52}53 54; Check the high end of the aligned STHY range.55define void @f6(ptr %dst, i16 %val) {56; CHECK-LABEL: f6:57; CHECK: sthy %r3, 524286(%r2)58; CHECK: br %r1459 %ptr = getelementptr i16, ptr %dst, i64 26214360 store i16 %val, ptr %ptr61 ret void62}63 64; Check the next halfword up, which needs separate address logic.65; Other sequences besides this one would be OK.66define void @f7(ptr %dst, i16 %val) {67; CHECK-LABEL: f7:68; CHECK: agfi %r2, 52428869; CHECK: sth %r3, 0(%r2)70; CHECK: br %r1471 %ptr = getelementptr i16, ptr %dst, i64 26214472 store i16 %val, ptr %ptr73 ret void74}75 76; Check the high end of the negative aligned STHY range.77define void @f8(ptr %dst, i16 %val) {78; CHECK-LABEL: f8:79; CHECK: sthy %r3, -2(%r2)80; CHECK: br %r1481 %ptr = getelementptr i16, ptr %dst, i64 -182 store i16 %val, ptr %ptr83 ret void84}85 86; Check the low end of the STHY range.87define void @f9(ptr %dst, i16 %val) {88; CHECK-LABEL: f9:89; CHECK: sthy %r3, -524288(%r2)90; CHECK: br %r1491 %ptr = getelementptr i16, ptr %dst, i64 -26214492 store i16 %val, ptr %ptr93 ret void94}95 96; Check the next halfword down, which needs separate address logic.97; Other sequences besides this one would be OK.98define void @f10(ptr %dst, i16 %val) {99; CHECK-LABEL: f10:100; CHECK: agfi %r2, -524290101; CHECK: sth %r3, 0(%r2)102; CHECK: br %r14103 %ptr = getelementptr i16, ptr %dst, i64 -262145104 store i16 %val, ptr %ptr105 ret void106}107 108; Check that STH allows an index.109define void @f11(i64 %dst, i64 %index, i16 %val) {110; CHECK-LABEL: f11:111; CHECK: sth %r4, 4094({{%r3,%r2|%r2,%r3}})112; CHECK: br %r14113 %add1 = add i64 %dst, %index114 %add2 = add i64 %add1, 4094115 %ptr = inttoptr i64 %add2 to ptr116 store i16 %val, ptr %ptr117 ret void118}119 120; Check that STHY allows an index.121define void @f12(i64 %dst, i64 %index, i16 %val) {122; CHECK-LABEL: f12:123; CHECK: sthy %r4, 4096({{%r3,%r2|%r2,%r3}})124; CHECK: br %r14125 %add1 = add i64 %dst, %index126 %add2 = add i64 %add1, 4096127 %ptr = inttoptr i64 %add2 to ptr128 store i16 %val, ptr %ptr129 ret void130}131