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1; Test 64-bit GPR accesses to a PC-relative location.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5@gsrc16 = dso_local global i16 16@gsrc32 = dso_local global i32 17@gsrc64 = dso_local global i64 18@gdst16 = dso_local global i16 29@gdst32 = dso_local global i32 210@gdst64 = dso_local global i64 211@gsrc16u = dso_local global i16 1, align 1, section "foo"12@gsrc32u = dso_local global i32 1, align 2, section "foo"13@gsrc64u = dso_local global i64 1, align 4, section "foo"14@gdst16u = dso_local global i16 2, align 1, section "foo"15@gdst32u = dso_local global i32 2, align 2, section "foo"16@gdst64u = dso_local global i64 2, align 4, section "foo"17 18; Check sign-extending loads from i16.19define dso_local i64 @f1() {20; CHECK-LABEL: f1:21; CHECK: lghrl %r2, gsrc1622; CHECK: br %r1423 %val = load i16, ptr@gsrc1624 %ext = sext i16 %val to i6425 ret i64 %ext26}27 28; Check zero-extending loads from i16.29define dso_local i64 @f2() {30; CHECK-LABEL: f2:31; CHECK: llghrl %r2, gsrc1632; CHECK: br %r1433 %val = load i16, ptr@gsrc1634 %ext = zext i16 %val to i6435 ret i64 %ext36}37 38; Check sign-extending loads from i32.39define dso_local i64 @f3() {40; CHECK-LABEL: f3:41; CHECK: lgfrl %r2, gsrc3242; CHECK: br %r1443 %val = load i32, ptr@gsrc3244 %ext = sext i32 %val to i6445 ret i64 %ext46}47 48; Check zero-extending loads from i32.49define dso_local i64 @f4() {50; CHECK-LABEL: f4:51; CHECK: llgfrl %r2, gsrc3252; CHECK: br %r1453 %val = load i32, ptr@gsrc3254 %ext = zext i32 %val to i6455 ret i64 %ext56}57 58; Check truncating 16-bit stores.59define dso_local void @f5(i64 %val) {60; CHECK-LABEL: f5:61; CHECK: sthrl %r2, gdst1662; CHECK: br %r1463 %half = trunc i64 %val to i1664 store i16 %half, ptr@gdst1665 ret void66}67 68; Check truncating 32-bit stores.69define dso_local void @f6(i64 %val) {70; CHECK-LABEL: f6:71; CHECK: strl %r2, gdst3272; CHECK: br %r1473 %word = trunc i64 %val to i3274 store i32 %word, ptr@gdst3275 ret void76}77 78; Check plain loads and stores.79define dso_local void @f7() {80; CHECK-LABEL: f7:81; CHECK: lgrl %r0, gsrc6482; CHECK: stgrl %r0, gdst6483; CHECK: br %r1484 %val = load i64, ptr@gsrc6485 store i64 %val, ptr@gdst6486 ret void87}88 89; Repeat f1 with an unaligned variable.90define dso_local i64 @f8() {91; CHECK-LABEL: f8:92; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT93; CHECK: lgh %r2, 0([[REG]])94; CHECK: br %r1495 %val = load i16, ptr@gsrc16u, align 196 %ext = sext i16 %val to i6497 ret i64 %ext98}99 100; Repeat f2 with an unaligned variable.101define dso_local i64 @f9() {102; CHECK-LABEL: f9:103; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT104; CHECK: llgh %r2, 0([[REG]])105; CHECK: br %r14106 %val = load i16, ptr@gsrc16u, align 1107 %ext = zext i16 %val to i64108 ret i64 %ext109}110 111; Repeat f3 with an unaligned variable.112define dso_local i64 @f10() {113; CHECK-LABEL: f10:114; CHECK: larl [[REG:%r[0-5]]], gsrc32u115; CHECK: lgf %r2, 0([[REG]])116; CHECK: br %r14117 %val = load i32, ptr@gsrc32u, align 2118 %ext = sext i32 %val to i64119 ret i64 %ext120}121 122; Repeat f4 with an unaligned variable.123define dso_local i64 @f11() {124; CHECK-LABEL: f11:125; CHECK: larl [[REG:%r[0-5]]], gsrc32u126; CHECK: llgf %r2, 0([[REG]])127; CHECK: br %r14128 %val = load i32, ptr@gsrc32u, align 2129 %ext = zext i32 %val to i64130 ret i64 %ext131}132 133; Repeat f5 with an unaligned variable.134define dso_local void @f12(i64 %val) {135; CHECK-LABEL: f12:136; CHECK: lgrl [[REG:%r[0-5]]], gdst16u@GOT137; CHECK: sth %r2, 0([[REG]])138; CHECK: br %r14139 %half = trunc i64 %val to i16140 store i16 %half, ptr@gdst16u, align 1141 ret void142}143 144; Repeat f6 with an unaligned variable.145define dso_local void @f13(i64 %val) {146; CHECK-LABEL: f13:147; CHECK: larl [[REG:%r[0-5]]], gdst32u148; CHECK: st %r2, 0([[REG]])149; CHECK: br %r14150 %word = trunc i64 %val to i32151 store i32 %word, ptr@gdst32u, align 2152 ret void153}154 155; Repeat f7 with unaligned variables.156define dso_local void @f14() {157; CHECK-LABEL: f14:158; CHECK: larl [[REG:%r[0-5]]], gsrc64u159; CHECK: lg [[VAL:%r[0-5]]], 0([[REG]])160; CHECK: larl [[REG:%r[0-5]]], gdst64u161; CHECK: stg [[VAL]], 0([[REG]])162; CHECK: br %r14163 %val = load i64, ptr@gsrc64u, align 4164 store i64 %val, ptr@gdst64u, align 4165 ret void166}167